Intel Workshop: HPC Code Modernization

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 Date: Thursday, Nov 19, 2015 8:00 - 20:00
Friday, Nov 20, 2015 8:00 - 17:30
Location: LRZ Building, University campus Garching, near Munich
Contents: The Intel® HPC Code Modernization Conference and Workshop is the leading event for Software Developers, Software Architects, Project Managers, R&D Directors and CxOs in HPC. It’s a unique opportunity to hear about future technology innovations in HPC from Intel – including next generation Intel® Xeon and Intel® Xeon Phi (aka Knights Landing) processors – and learn actionable content to create, modernize and optimize high-performance parallel code in C / C++ or Fortran.

Learn from experts during in depth technical sessions and real world case studies. Join us for 2 days of conferences and advanced workshops!

  • INTEL TECHNOLOGY PLATFORM FOR HPC & PROCESSOR UPDATE
  • MEET INTEL PARALLEL STUDIO XE 2016 – WHAT’S NEW?
  • HPC MEETS BIG DATA – CODING HIGH-PERFORMANCE ANALYTICS IN C++ USING INTEL’S NEW DATA ANALYTICS ACCELERATION LIBRARY
  • OPTIMIZE AND PERFORM WITH INTEL MPI
  • BEST PRACTICES FOR VECTORIZATION – PARALLELISM AT CORE LEVEL (SIMD)
  • MAXIMIZING PERFORMANCE AND SCALABILITY USING PERFORMANCE LIBRARIES
  • REAL WORLD EXAMPLES FOR VECTORIZATION
  • CASE STUDY – DYNAMIC LOAD BALANCING OF THE N-BODY PROBLEM
  • CASE STUDY – PERFORMANCE OPTIMIZATION OF BLACK-SCHOLES CALCULATION
  • CASE STUDY – CODE MODERNIZATION OF POLYHEDRON BENCHMARK SUITE
  • CASE STUDY – IMPROVING PERFORMANCE OF NUMERICAL WEATHER PREDICTION CODES
  • CASE STUDY – PAIRWISE SEQUENCE ALIGNMENT WITH THE SMITH-WATERMAN ALGORITHM
  • CASE STUDY – CODE OPTIMIZATION IN A 3D DIFFUSION MODEL
Details:

see: Fyler from Intel
Prerequisites Participants must have good knowledge in Fortran or C and in parallel programming
Language: English
Teachers: from Intel
Registration: Via Intel: http://www.inteldevconference.com -> http://www.inteldevconference.com/events/munich-germany-2/