Performance Counters Complete List

Description	vtune	lipfpm, histx	pfmon, profile.pl, i2prof.pl, qprofile
Full Pipe Bubbles in Main Pipe -- L1D_FPU or RSE.	`BACK_END_BUBBLE-L1D_FPU_ RSE`	`BACK_END_BUBBLE.L1D_FPU_ RSE`	`BACK_END_BUBBLE_L1D_FPU_ RSE`
ALAT Entry Replaced -- both integer and floating point instructions	`ALAT_CAPACITY_MISS-ALL`	`ALAT_CAPACITY_MISS.ALL`	`ALAT_CAPACITY_MISS_ALL`
ALAT Entry Replaced -- only floating point instructions	`ALAT_CAPACITY_MISS-FP`	`ALAT_CAPACITY_MISS.FP`	`ALAT_CAPACITY_MISS_FP`
ALAT Entry Replaced -- only integer instructions	`ALAT_CAPACITY_MISS-INT`	`ALAT_CAPACITY_MISS.INT`	`ALAT_CAPACITY_MISS_INT`
Full Pipe Bubbles in Main Pipe -- Front-end, RSE, EXE, FPU/L1D stall or a pipeline flush due to an exception/branch misprediction	`BACK_END_BUBBLE-ALL`	`BACK_END_BUBBLE.ALL`	`BACK_END_BUBBLE_ALL`
Full Pipe Bubbles in Main Pipe -- front-end	`BACK_END_BUBBLE-FE`	`BACK_END_BUBBLE.FE`	`BACK_END_BUBBLE_FE`
Full Pipe Bubbles in Main Pipe -- L1D_FPU or RSE.	`BACK_END_BUBBLE-L1D_FPU_ RSE`	`BACK_END_BUBBLE.L1D_FPU_ RSE`	`BACK_END_BUBBLE_L1D_FPU_ RSE`
	`BACK_END_BUBBLE-NONE`
BE Branch Misprediction Detail -- any back-end (be) mispredictions	`BE_BR_MISPRED_DETAIL-ANY`	`BE_BR_MISPRED_DETAIL.ANY`	`BE_BR_MISPRED_DETAIL_ANY`
BE Branch Misprediction Detail -- only back-end pfs mispredictions for taken branches	`BE_BR_MISPRED_DETAIL-PFS`	`BE_BR_MISPRED_DETAIL.PFS`	`BE_BR_MISPRED_DETAIL_PFS`
BE Branch Misprediction Detail -- only back-end rotate mispredictions	`BE_BR_MISPRED_DETAIL-ROT`	`BE_BR_MISPRED_DETAIL.ROT`	`BE_BR_MISPRED_DETAIL_ROT`
BE Branch Misprediction Detail -- only back-end stage mispredictions	`BE_BR_MISPRED_DETAIL-STG`	`BE_BR_MISPRED_DETAIL.STG`	`BE_BR_MISPRED_DETAIL_STG`
Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe	`BE_EXE_BUBBLE-ALL`	`BE_EXE_BUBBLE.ALL`	`BE_EXE_BUBBLE_ALL`
Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to AR or CR dependency Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- ARCR, PR, CANCEL or BANK_SWITCH	`BE_EXE_BUBBLE-ARCR`	`BE_EXE_BUBBLE.ARCR`	`BE_EXE_BUBBLE_ARCR`
Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- ARCR, PR, CANCEL or BANK_SWITCH	`BE_EXE_BUBBLE-ARCR_PR_ CANCEL_BANK`	`BE_EXE_BUBBLE.ARCR_PR_ CANCEL_BANK`	`BE_EXE_BUBBLE_ARCR_PR_ CANCEL_BANK`
Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to bank switching.	`BE_EXE_BUBBLE-BANK_ SWITCH`	`BE_EXE_BUBBLE.BANK_ SWITCH`	`BE_EXE_BUBBLE_BANK_ SWITCH`
Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to a canceled load	`BE_EXE_BUBBLE-CANCEL`	`BE_EXE_BUBBLE.CANCEL`	`BE_EXE_BUBBLE_CANCEL`
Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to FR/FR or FR/load dependency	`BE_EXE_BUBBLE-FRALL`	`BE_EXE_BUBBLE.FRALL`	`BE_EXE_BUBBLE_FRALL`
Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to GR/GR or GR/load dependency	`BE_EXE_BUBBLE-GRALL`	`BE_EXE_BUBBLE.GRALL`	`BE_EXE_BUBBLE_GRALL`
Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to GR/GR dependency	`BE_EXE_BUBBLE-GRGR`	`BE_EXE_BUBBLE.GRGR`	`BE_EXE_BUBBLE_GRGR`
	`BE_EXE_BUBBLE-NONE`
Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to PR dependency	`BE_EXE_BUBBLE-PR`	`BE_EXE_BUBBLE.PR`	`BE_EXE_BUBBLE_PR`
Full Pipe Bubbles in Main Pipe due to Flushes -- Back-end was stalled due to either an exception/interruption or branch misprediction flush	`BE_FLUSH_BUBBLE-ALL`	`BE_FLUSH_BUBBLE.ALL`	`BE_FLUSH_BUBBLE_ALL`
Full Pipe Bubbles in Main Pipe due to Flushes -- Back-end was stalled due to a branch misprediction flush	`BE_FLUSH_BUBBLE-BRU`	`BE_FLUSH_BUBBLE.BRU`	`BE_FLUSH_BUBBLE_BRU`
	`BE_FLUSH_BUBBLE-NONE`
Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to an exception/interruption flush	`BE_FLUSH_BUBBLE-XPN`	`BE_FLUSH_BUBBLE.XPN`	`BE_FLUSH_BUBBLE_XPN`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D or FPU	`BE_L1D_FPU_BUBBLE-ALL`	`BE_L1D_FPU_BUBBLE.ALL`	`BE_L1D_FPU_BUBBLE_ALL`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by FPU.	`BE_L1D_FPU_BUBBLE-FPU`	`BE_L1D_FPU_BUBBLE.FPU`	`BE_L1D_FPU_BUBBLE_FPU`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D.	`BE_L1D_FPU_BUBBLE-L1D`	`BE_L1D_FPU_BUBBLE.L1D`	`BE_L1D_FPU_BUBBLE_L1D`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to DCS requiring a stall	`BE_L1D_FPU_BUBBLE-L1D_DCS`	`BE_L1D_FPU_BUBBLE.L1D_DCS`	`BE_L1D_FPU_BUBBLE_L1D_DCS`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to DCU recirculating	`BE_L1D_FPU_BUBBLE-L1D_ DCURECIR`	`BE_L1D_FPU_BUBBLE.L1D_ DCURECIR`	`BE_L1D_FPU_BUBBLE_L1D_ DCURECIR`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due a store in conflict with a returning fill.	`BE_L1D_FPU_BUBBLE-L1D_ FILLCONF`	`BE_L1D_FPU_BUBBLE.L1D_ FILLCONF`	`BE_L1D_FPU_BUBBLE_L1D_ FILLCONF`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to store buffer being full	`BE_L1D_FPU_BUBBLE-L1D_ FULLSTBUF`	`BE_L1D_FPU_BUBBLE.L1D_ FULLSTBUF`	`BE_L1D_FPU_BUBBLE_L1D_ FULLSTBUF`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to Hardware Page Walker	`BE_L1D_FPU_BUBBLE-L1D_HPW`	`BE_L1D_FPU_BUBBLE.L1D_HPW`	`BE_L1D_FPU_BUBBLE_L1D_ HPW`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L2 Back Pressure	`BE_L1D_FPU_BUBBLE-L1D_ L2BPRESS`	`BE_L1D_FPU_BUBBLE.L1D_ L2BPRESS`	`BE_L1D_FPU_BUBBLE_L1D_ L2BPRESS`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to architectural ordering conflict	`BE_L1D_FPU_BUBBLE-L1D_ LDCHK`	`BE_L1D_FPU_BUBBLE.L1D_ LDCHK`	`BE_L1D_FPU_BUBBLE_L1D_ LDCHK`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to architectural ordering conflict	`BE_L1D_FPU_BUBBLE-L1D_ LDCONF`	`BE_L1D_FPU_BUBBLE.L1D_ LDCONF`	`BE_L1D_FPU_BUBBLE_L1D_ LDCONF`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L1D data return needing recirculated NaT generation. Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to ld8.fill conflict with st8.spill not written to unat.	`BE_L1D_FPU_BUBBLE-L1D_ NAT`	`BE_L1D_FPU_BUBBLE.L1D_ NAT`	`BE_L1D_FPU_BUBBLE_L1D_ NAT`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to ld8.fill conflict with st8.spill not written to unat.	`BE_L1D_FPU_BUBBLE-L1D_ NATCONF`	`BE_L1D_FPU_BUBBLE.L1D_ NATCONF`	`BE_L1D_FPU_BUBBLE_L1D_ NATCONF`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to store buffer cancel needing recirculate.	`BE_L1D_FPU_BUBBLE-L1D_ STBUFRECIR`	`BE_L1D_FPU_BUBBLE.L1D_ STBUFRECIR`	`BE_L1D_FPU_BUBBLE_L1D_ STBUFRECIR`
Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L2DTLB to L1DTLB transfer	`BE_L1D_FPU_BUBBLE-L1D_TLB`	`BE_L1D_FPU_BUBBLE.L1D_TLB`	`BE_L1D_FPU_BUBBLE_L1D_TLB`
Invalid Bundles if BE Not Stalled for Other Reasons. -- count regardless of cause Invalid Bundles at the Exit from IB -- count regardless of cause	`BE_LOST_BW_DUE_TO_FE-ALL`	`BE_LOST_BW_DUE_TO_FE.ALL`	`BE_LOST_BW_DUE_TO_FE_ALL`
Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch initialization stall Invalid Bundles at the Exit from IB -- only if caused by branch initialization stall	`BE_LOST_BW_DUE_TO_FE-BI`	`BE_LOST_BW_DUE_TO_FE.BI`	`BE_LOST_BW_DUE_TO_FE_BI`
Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch retirement queue stall Invalid Bundles at the Exit from IB -- only if caused by branch retirement queue stall	`BE_LOST_BW_DUE_TO_FE-BRQ`	`BE_LOST_BW_DUE_TO_FE.BRQ`	`BE_LOST_BW_DUE_TO_FE_BRQ`
Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch interlock stall Invalid Bundles at the Exit from IB -- only if caused by branch interlock stall	`BE_LOST_BW_DUE_TO_FE-BR_ ILOCK`	`BE_LOST_BW_DUE_TO_FE.BR_ ILOCK`	`BE_LOST_BW_DUE_TO_FE_BR_ ILOCK`
Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch resteer bubble stall Invalid Bundles at the Exit from IB -- only if caused by branch resteer bubble stall	`BE_LOST_BW_DUE_TO_ FE-BUBBLE`	`BE_LOST_BW_DUE_TO_ FE.BUBBLE`	`BE_LOST_BW_DUE_TO_ FE_BUBBLE`
Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by a front-end flush Invalid Bundles at the Exit from IB -- only if caused by a front-end flush	`BE_LOST_BW_DUE_TO_ FE-FEFLUSH`	`BE_LOST_BW_DUE_TO_ FE.FEFLUSH`	`BE_LOST_BW_DUE_TO_ FE_FEFLUSH`
Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by a recirculate for a cache line fill operation Invalid Bundles at the Exit from IB -- only if caused by a recirculate for a cache line fill operation	`BE_LOST_BW_DUE_TO_FE-FILL_ RECIRC`	`BE_LOST_BW_DUE_TO_FE.FILL_ RECIRC`	`BE_LOST_BW_DUE_TO_FE_FILL_ RECIRC`
Invalid Bundles if BE Not Stalled for Other Reasons. -- (* meaningless for this event ) Invalid Bundles at the Exit from IB -- ( meaningless for this event *)	`BE_LOST_BW_DUE_TO_ FE-IBFULL`	`BE_LOST_BW_DUE_TO_ FE.IBFULL`	`BE_LOST_BW_DUE_TO_ FE_IBFULL`
Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by instruction cache miss stall Invalid Bundles at the Exit from IB -- only if caused by instruction cache miss stall	`BE_LOST_BW_DUE_TO_ FE-IMISS`	`BE_LOST_BW_DUE_TO_ FE.IMISS`	`BE_LOST_BW_DUE_TO_ FE_IMISS`
Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by perfect loop prediction stall Invalid Bundles at the Exit from IB -- only if caused by perfect loop prediction stall	`BE_LOST_BW_DUE_TO_FE-PLP`	`BE_LOST_BW_DUE_TO_FE.PLP`	`BE_LOST_BW_DUE_TO_FE_PLP`
Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by TLB stall Invalid Bundles at the Exit from IB -- only if caused by TLB stall	`BE_LOST_BW_DUE_TO_ FE-TLBMISS`	`BE_LOST_BW_DUE_TO_ FE.TLBMISS`	`BE_LOST_BW_DUE_TO_ FE_TLBMISS`
Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by unreachable bundle Invalid Bundles at the Exit from IB -- only if caused by unreachable bundle	`BE_LOST_BW_DUE_TO_ FE-UNREACHED`	`BE_LOST_BW_DUE_TO_ FE.UNREACHED`	`BE_LOST_BW_DUE_TO_ FE_UNREACHED`
Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE	`BE_RSE_BUBBLE-ALL`	`BE_RSE_BUBBLE.ALL`	`BE_RSE_BUBBLE_ALL`
Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to AR dependencies	`BE_RSE_BUBBLE-AR_DEP`	`BE_RSE_BUBBLE.AR_DEP`	`BE_RSE_BUBBLE_AR_DEP`
Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to bank switching	`BE_RSE_BUBBLE-BANK_SWITCH`	`BE_RSE_BUBBLE.BANK_SWITCH`	`BE_RSE_BUBBLE_BANK_SWITCH`
Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to loadrs calculations	`BE_RSE_BUBBLE-LOADRS`	`BE_RSE_BUBBLE.LOADRS`	`BE_RSE_BUBBLE_LOADRS`
	`BE_RSE_BUBBLE-NONE`
Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to need to spill	`BE_RSE_BUBBLE-OVERFLOW`	`BE_RSE_BUBBLE.OVERFLOW`	`BE_RSE_BUBBLE_OVERFLOW`
Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to need to fill	`BE_RSE_BUBBLE-UNDERFLOW`	`BE_RSE_BUBBLE.UNDERFLOW`	`BE_RSE_BUBBLE_UNDERFLOW`
Branch Event Captured	`BRANCH_EVENT`		`BRANCH_EVENT`
FE Branch Mispredict Detail -- All branch types regardless of prediction result Number of Encoded Branches Retired -- All encoded branches regardless of prediction result	`BR_MISPRED_DETAIL-ALL-ALL_ PRED`	`BR_MISPRED_DETAIL.ALL.ALL_ PRED`	`BR_MISPRED_DETAIL_ALL_ ALL_PRED`
FE Branch Mispredict Detail -- All branch types, correctly predicted branches (outcome and target) Number of Encoded Branches Retired -- All encoded branches, correctly predicted branches (outcome and target)	`BR_MISPRED_DETAIL-ALL- CORRECT_PRED`	`BR_MISPRED_DETAIL.ALL. CORRECT_PRED`	`BR_MISPRED_DETAIL_ALL_ CORRECT_PRED`
FE Branch Mispredict Detail -- All branch types, mispredicted branches due to wrong branch direction Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong branch direction	`BR_MISPRED_DETAIL-ALL- WRONG_PATH`	`BR_MISPRED_DETAIL.ALL. WRONG_PATH`	`BR_MISPRED_DETAIL_ALL_ WRONG_PATH`
FE Branch Mispredict Detail -- All branch types, mispredicted branches due to wrong target for taken branches Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong target for taken branches	`BR_MISPRED_DETAIL-ALL- WRONG_TARGET`	`BR_MISPRED_DETAIL.ALL. WRONG_TARGET`	`BR_MISPRED_DETAIL_ALL_ WRONG_TARGET`
FE Branch Mispredict Detail -- Only IP relative branches, regardless of prediction result	`BR_MISPRED_DETAIL-IPREL- ALL_PRED`	`BR_MISPRED_DETAIL.IPREL. ALL_PRED`	`BR_MISPRED_DETAIL_IPREL_ ALL_PRED`
FE Branch Mispredict Detail -- Only IP relative branches, correctly predicted branches (outcome and target)	`BR_MISPRED_DETAIL-IPREL- CORRECT_PRED`	`BR_MISPRED_DETAIL.IPREL. CORRECT_PRED`	`BR_MISPRED_DETAIL_IPREL_ CORRECT_PRED`
FE Branch Mispredict Detail -- Only IP relative branches, mispredicted branches due to wrong branch direction	`BR_MISPRED_DETAIL-IPREL- WRONG_PATH`	`BR_MISPRED_DETAIL.IPREL. WRONG_PATH`	`BR_MISPRED_DETAIL_IPREL_ WRONG_PATH`
FE Branch Mispredict Detail -- Only IP relative branches, mispredicted branches due to wrong target for taken branches	`BR_MISPRED_DETAIL-IPREL- WRONG_TARGET`	`BR_MISPRED_DETAIL.IPREL. WRONG_TARGET`	`BR_MISPRED_DETAIL_IPREL_ WRONG_TARGET`
FE Branch Mispredict Detail -- Only non-return indirect branches, regardless of prediction result	`BR_MISPRED_DETAIL-NTRETIND- ALL_PRED`	`BR_MISPRED_DETAIL.NTRETIND. ALL_PRED`	`BR_MISPRED_DETAIL_NTRETIND_ ALL_PRED`
FE Branch Mispredict Detail -- Only non-return indirect branches, correctly predicted branches (outcome and target)	`BR_MISPRED_DETAIL-NTRETIND- CORRECT_PRED`	`BR_MISPRED_DETAIL.NTRETIND. CORRECT_PRED`	`BR_MISPRED_DETAIL_NTRETIND_ CORRECT_PRED`
FE Branch Mispredict Detail -- Only non-return indirect branches, mispredicted branches due to wrong branch direction	`BR_MISPRED_DETAIL-NTRETIND- WRONG_PATH`	`BR_MISPRED_DETAIL.NTRETIND. WRONG_PATH`	`BR_MISPRED_DETAIL_NTRETIND_ WRONG_PATH`
FE Branch Mispredict Detail -- Only non-return indirect branches, mispredicted branches due to wrong target for taken branches	`BR_MISPRED_DETAIL-NTRETIND- WRONG_TARGET`	`BR_MISPRED_DETAIL.NTRETIND. WRONG_TARGET`	`BR_MISPRED_DETAIL_NTRETIND_ WRONG_TARGET`
FE Branch Mispredict Detail -- Only return type branches, regardless of prediction result	`BR_MISPRED_DETAIL-RETURN- ALL_PRED`	`BR_MISPRED_DETAIL.RETURN. ALL_PRED`	`BR_MISPRED_DETAIL_RETURN_ ALL_PRED`
FE Branch Mispredict Detail -- Only return type branches, correctly predicted branches (outcome and target)	`BR_MISPRED_DETAIL-RETURN- CORRECT_PRED`	`BR_MISPRED_DETAIL.RETURN. CORRECT_PRED`	`BR_MISPRED_DETAIL_RETURN_ CORRECT_PRED`
FE Branch Mispredict Detail -- Only return type branches, mispredicted branches due to wrong branch direction	`BR_MISPRED_DETAIL-RETURN- WRONG_PATH`	`BR_MISPRED_DETAIL.RETURN. WRONG_PATH`	`BR_MISPRED_DETAIL_RETURN_ WRONG_PATH`
FE Branch Mispredict Detail -- Only return type branches, mispredicted branches due to wrong target for taken branches	`BR_MISPRED_DETAIL-RETURN- WRONG_TARGET`	`BR_MISPRED_DETAIL.RETURN. WRONG_TARGET`	`BR_MISPRED_DETAIL_RETURN_ WRONG_TARGET`
FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction	`BR_MISPRED_DETAIL2-ALL-ALL_ UNKNOWN_PRED`	`BR_MISPRED_DETAIL2.ALL.ALL_ UNKNOWN_PRED`	`BR_MISPRED_DETAIL2_ALL_ALL_ UNKNOWN_PRED`
	`BR_MISPRED_DETAIL2-ALL-NONE`
FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction and correctly predicted branch (outcome & target)	`BR_MISPRED_DETAIL2-ALL- UNKNOWN_PATH_CORRECT_PRED`	`BR_MISPRED_DETAIL2.ALL. UNKNOWN_PATH_CORRECT_PRED`	`BR_MISPRED_DETAIL2_ALL_ UNKNOWN_PATH_CORRECT_PRED`
FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction and wrong branch direction	`BR_MISPRED_DETAIL2-ALL- UNKNOWN_PATH_WRONG_PATH`	`BR_MISPRED_DETAIL2.ALL. UNKNOWN_PATH_WRONG_PATH`	`BR_MISPRED_DETAIL2_ALL_ UNKNOWN_PATH_WRONG_PATH`
FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction	BR_MISPRED_DETAIL2-IPREL- ALL_UNKNOWN_PRED	BR_MISPRED_DETAIL2.IPREL. ALL_UNKNOWN_PRED	BR_MISPRED_DETAIL2_IPREL_ ALL_UNKNOWN_PRED
	`BR_MISPRED_DETAIL2-IPREL- NONE`
FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction and correct predicted branch (outcome & target)	`BR_MISPRED_DETAIL2-IPREL- UNKNOWN_PATH_CORRECT_PRED`	`BR_MISPRED_DETAIL2.IPREL. UNKNOWN_PATH_CORRECT_PRED`	`BR_MISPRED_DETAIL2_IPREL_ UNKNOWN_PATH_CORRECT_PRED`
FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction and wrong branch direction	`BR_MISPRED_DETAIL2-IPREL- UNKNOWN_PATH_WRONG_PATH`	`BR_MISPRED_DETAIL2.IPREL. UNKNOWN_PATH_WRONG_PATH`	`BR_MISPRED_DETAIL2_IPREL_ UNKNOWN_PATH_WRONG_PATH`
FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction	`BR_MISPRED_DETAIL2-NRETIND- ALL_UNKNOWN_PRED`	`BR_MISPRED_DETAIL2.NRETIND. ALL_UNKNOWN_PRED`	`BR_MISPRED_DETAIL2_NRETIND_ ALL_UNKNOWN_PRED`
	`BR_MISPRED_DETAIL2-NRETIND- NONE`
FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction and correct predicted branch (outcome & target)	`BR_MISPRED_DETAIL2-NRETIND- UNKNOWN_PATH_CORRECT_PRED`	`BR_MISPRED_DETAIL2.NRETIND. UNKNOWN_PATH_CORRECT_PRED`	`BR_MISPRED_DETAIL2_NRETIND_ UNKNOWN_PATH_CORRECT_PRED`
FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction and wrong branch direction	`BR_MISPRED_DETAIL2-NRETIND- UNKNOWN_PATH_WRONG_PATH`	`BR_MISPRED_DETAIL2.NRETIND. UNKNOWN_PATH_WRONG_PATH`	`BR_MISPRED_DETAIL2_NRETIND_ UNKNOWN_PATH_WRONG_PATH`
FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction	`BR_MISPRED_DETAIL2-RETURN- ALL_UNKNOWN_PRED`	`BR_MISPRED_DETAIL2.RETURN. ALL_UNKNOWN_PRED`	`BR_MISPRED_DETAIL2_RETURN_ ALL_UNKNOWN_PRED`
	`BR_MISPRED_DETAIL2-RETURN- NONE`
FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction and correct predicted branch (outcome & target)	`BR_MISPRED_DETAIL2-RETURN- UNKNOWN_PATH_CORRECT_PRED`	`BR_MISPRED_DETAIL2.RETURN. UNKNOWN_PATH_CORRECT_PRED`	`BR_MISPRED_DETAIL2_RETURN_ UNKNOWN_PATH_CORRECT_PRED`
FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction and wrong branch direction	`BR_MISPRED_DETAIL2-RETURN- UNKNOWN_PATH_WRONG_PATH`	`BR_MISPRED_DETAIL2.RETURN. UNKNOWN_PATH_WRONG_PATH`	`BR_MISPRED_DETAIL2_RETURN_ UNKNOWN_PATH_WRONG_PATH`
FE Branch Path Prediction Detail -- All branch types, incorrectly predicted path and not taken branch	`BR_PATH_PRED-ALL-MISPRED_ NOTTAKEN`	`BR_PATH_PRED.ALL.MISPRED_ NOTTAKEN`	`BR_PATH_PRED_ALL_MISPRED_ NOTTAKEN`
FE Branch Path Prediction Detail -- All branch types, incorrectly predicted path and taken branch	`BR_PATH_PRED-ALL-MISPRED_ TAKEN`	`BR_PATH_PRED.ALL.MISPRED_ TAKEN`	`BR_PATH_PRED_ALL_MISPRED_ TAKEN`
FE Branch Path Prediction Detail -- All branch types, correctly predicted path and not taken branch	`BR_PATH_PRED-ALL-OKPRED_ NOTTAKEN`	`BR_PATH_PRED.ALL.OKPRED_ NOTTAKEN`	`BR_PATH_PRED_ALL_OKPRED_ NOTTAKEN`
FE Branch Path Prediction Detail -- All branch types, correctly predicted path and taken branch	`BR_PATH_PRED-ALL-OKPRED_ TAKEN`	`BR_PATH_PRED.ALL.OKPRED_ TAKEN`	`BR_PATH_PRED_ALL_OKPRED_ TAKEN`
FE Branch Path Prediction Detail -- Only IP relative branches, incorrectly predicted path and not taken branch	`BR_PATH_PRED-IPREL-MISPRED_ NOTTAKEN`	`BR_PATH_PRED.IPREL.MISPRED_ NOTTAKEN`	`BR_PATH_PRED_IPREL_MISPRED_ NOTTAKEN`
FE Branch Path Prediction Detail -- Only IP relative branches, incorrectly predicted path and taken branch	`BR_PATH_PRED-IPREL-MISPRED_ TAKEN`	`BR_PATH_PRED.IPREL.MISPRED_ TAKEN`	`BR_PATH_PRED_IPREL_MISPRED_ TAKEN`
FE Branch Path Prediction Detail -- Only IP relative branches, correctly predicted path and not taken branch	`BR_PATH_PRED-IPREL-OKPRED_ NOTTAKEN`	`BR_PATH_PRED.IPREL.OKPRED_ NOTTAKEN`	`BR_PATH_PRED_IPREL_OKPRED_ NOTTAKEN`
FE Branch Path Prediction Detail -- Only IP relative branches, correctly predicted path and taken branch	`BR_PATH_PRED-IPREL-OKPRED_ TAKEN`	`BR_PATH_PRED.IPREL.OKPRED_ TAKEN`	`BR_PATH_PRED_IPREL_OKPRED_ TAKEN`
FE Branch Path Prediction Detail -- Only non-return indirect branches, incorrectly predicted path and not taken branch	`BR_PATH_PRED-NRETIND-MISPRED_ NOTTAKEN`	`BR_PATH_PRED.NRETIND.MISPRED_ NOTTAKEN`	`BR_PATH_PRED_NRETIND_MISPRED_ NOTTAKEN`
FE Branch Path Prediction Detail -- Only non-return indirect branches, incorrectly predicted path and taken branch	`BR_PATH_PRED-NRETIND-MISPRED_ TAKEN`	`BR_PATH_PRED.NRETIND.MISPRED_ TAKEN`	`BR_PATH_PRED_NRETIND_MISPRED_ TAKEN`
FE Branch Path Prediction Detail -- Only non-return indirect branches, correctly predicted path and not taken branch	`BR_PATH_PRED-NRETIND-OKPRED_ NOTTAKEN`	`BR_PATH_PRED.NRETIND.OKPRED_ NOTTAKEN`	`BR_PATH_PRED_NRETIND_OKPRED_ NOTTAKEN`
FE Branch Path Prediction Detail -- Only non-return indirect branches, correctly predicted path and taken branch	`BR_PATH_PRED-NRETIND-OKPRED_ TAKEN`	`BR_PATH_PRED.NRETIND.OKPRED_ TAKEN`	`BR_PATH_PRED_NRETIND_OKPRED_ TAKEN`
FE Branch Path Prediction Detail -- Only return type branches, incorrectly predicted path and not taken branch	`BR_PATH_PRED-RETURN-MISPRED_ NOTTAKEN`	`BR_PATH_PRED.RETURN.MISPRED_ NOTTAKEN`	`BR_PATH_PRED_RETURN_MISPRED_ NOTTAKEN`
FE Branch Path Prediction Detail -- Only return type branches, incorrectly predicted path and taken branch	`BR_PATH_PRED-RETURN-MISPRED_ TAKEN`	`BR_PATH_PRED.RETURN.MISPRED_ TAKEN`	`BR_PATH_PRED_RETURN_MISPRED_ TAKEN`
FE Branch Path Prediction Detail -- Only return type branches, correctly predicted path and not taken branch	`BR_PATH_PRED-RETURN-OKPRED_ NOTTAKEN`	`BR_PATH_PRED.RETURN.OKPRED_ NOTTAKEN`	`BR_PATH_PRED_RETURN_OKPRED_ NOTTAKEN`
FE Branch Path Prediction Detail -- Only return type branches, correctly predicted path and taken branch	`BR_PATH_PRED-RETURN-OKPRED_ TAKEN`	`BR_PATH_PRED.RETURN.OKPRED_ TAKEN`	`BR_PATH_PRED_RETURN_OKPRED_ TAKEN`
FE Branch Path Prediction Detail (Unknown pred component) -- All branch types, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)	`BR_PATH_PRED2-ALL- UNKNOWNPRED_NOTTAKEN`	`BR_PATH_PRED2.ALL. UNKNOWNPRED_NOTTAKEN`	`BR_PATH_PRED2_ALL_ UNKNOWNPRED_NOTTAKEN`
FE Branch Path Prediction Detail (Unknown pred component) -- All branch types, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)	`BR_PATH_PRED2-ALL- UNKNOWNPRED_TAKEN`	`BR_PATH_PRED2.ALL. UNKNOWNPRED_TAKEN`	`BR_PATH_PRED2_ALL_ UNKNOWNPRED_TAKEN`
FE Branch Path Prediction Detail (Unknown pred component) -- Only IP relative branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)	`BR_PATH_PRED2-IPREL- UNKNOWNPRED_NOTTAKEN`	`BR_PATH_PRED2.IPREL. UNKNOWNPRED_NOTTAKEN`	`BR_PATH_PRED2_IPREL_ UNKNOWNPRED_NOTTAKEN`
FE Branch Path Prediction Detail (Unknown pred component) -- Only IP relative branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)	`BR_PATH_PRED2-IPREL- UNKNOWNPRED_TAKEN`	`BR_PATH_PRED2.IPREL. UNKNOWNPRED_TAKEN`	`BR_PATH_PRED2_IPREL_ UNKNOWNPRED_TAKEN`
FE Branch Path Prediction Detail (Unknown pred component) -- Only non-return indirect branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)	`BR_PATH_PRED2- NRETIND-UNKNOWNPRED_NOTTAKEN`	`BR_PATH_PRED2. NRETIND.UNKNOWNPRED_NOTTAKEN`	`BR_PATH_PRED2_NRETIND_ UNKNOWNPRED_NOTTAKEN`
FE Branch Path Prediction Detail (Unknown pred component) -- Only non-return indirect branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)	`BR_PATH_PRED2-NRETIND- UNKNOWNPRED_TAKEN`	`BR_PATH_PRED2.NRETIND. UNKNOWNPRED_TAKEN`	`BR_PATH_PRED2_NRETIND_ UNKNOWNPRED_TAKEN`
FE Branch Path Prediction Detail (Unknown pred component) -- Only return type branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)	`BR_PATH_PRED2-RETURN- UNKNOWNPRED_NOTTAKEN`	`BR_PATH_PRED2.RETURN. UNKNOWNPRED_NOTTAKEN`	`BR_PATH_PRED2_RETURN_ UNKNOWNPRED_NOTTAKEN`
FE Branch Path Prediction Detail (Unknown pred component) -- Only return type branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)	`BR_PATH_PRED2-RETURN- UNKNOWNPRED_TAKEN`	`BR_PATH_PRED2.RETURN. UNKNOWNPRED_TAKEN`	`BR_PATH_PRED2_RETURN_ UNKNOWNPRED_TAKEN`
Bus Transactions -- CPU or non-CPU (all transactions).	`BUS_ALL-ANY`	`BUS_ALL.ANY`	`BUS_ALL_ANY`
Bus Transactions -- non-CPU priority agents	`BUS_ALL-IO`	`BUS_ALL.IO`	`BUS_ALL_IO`
Bus Transactions -- local processor	`BUS_ALL-NONE`	`BUS_ALL.SELF`	`BUS_ALL_SELF`
	`BUS_ALL-SELF`
Bus Back Snoop Requests -- Counts the number of bus back snoop me requests	`BUS_BACKSNP_REQ-THIS`	`BUS_BACKSNP_REQ.THIS`	`BUS_BACKSNP_REQ_THIS`
BRQ Live Requests (upper 2 bits)	`BUS_BRQ_LIVE_REQ_HI`	`BUS_BRQ_LIVE_REQ_HI`	`BUS_BRQ_LIVE_REQ_HI`
BRQ Live Requests (lower 3 bits)	`BUS_BRQ_LIVE_REQ_LO`	`BUS_BRQ_LIVE_REQ_LO`	`BUS_BRQ_LIVE_REQ_LO`
BRQ Requests Inserted	`BUS_BRQ_REQ_INSERTED`	`BUS_BRQ_REQ_INSERTED`	`BUS_BRQ_REQ_INSERTED`
Valid Data Cycle on the Bus	`BUS_DATA_CYCLE`	`BUS_DATA_CYCLE`	`BUS_DATA_CYCLE`
Bus Hit Modified Line Transactions	`BUS_HITM`	`BUS_HITM`	`BUS_HITM`
IA-32 Compatible IO Bus Transactions -- CPU or non-CPU (all transactions).	`BUS_IO-ANY`	`BUS_IO.ANY`	`BUS_IO_ANY`
IA-32 Compatible IO Bus Transactions -- non-CPU priority agents	`BUS_IO-IO`	`BUS_IO.IO`	`BUS_IO_IO`
	`BUS_IO-NONE`
IA-32 Compatible IO Bus Transactions -- local processor	`BUS_IO-SELF`	`BUS_IO.SELF`	`BUS_IO_SELF`
Inorder Bus Queue Requests (upper 2 bits)	`BUS_IOQ_LIVE_REQ_HI`	`BUS_IOQ_LIVE_REQ_HI`	`BUS_IOQ_LIVE_REQ_HI`
Inorder Bus Queue Requests (lower2 bitst)	`BUS_IOQ_LIVE_REQ_LO`	`BUS_IOQ_LIVE_REQ_LO`	`BUS_IOQ_LIVE_REQ_LO`
IA-32 Compatible Bus Lock Transactions -- CPU or non-CPU (all transactions).	`BUS_LOCK-ANY`	`BUS_LOCK.ANY`	`BUS_LOCK_ANY`
	`BUS_LOCK-NONE`
IA-32 Compatible Bus Lock Transactions -- local processor	`BUS_LOCK-SELF`	`BUS_LOCK.SELF`	`BUS_LOCK_SELF`
Bus Memory Transactions -- All bus transactions from CPU or non-CPU (all transactions).	`BUS_MEMORY-ALL-ANY`	`BUS_MEMORY.ALL.ANY`	`BUS_MEMORY_ALL_ANY`
Bus Memory Transactions -- All bus transactions from non-CPU priority agents	`BUS_MEMORY-ALL-IO`	`BUS_MEMORY.ALL.IO`	`BUS_MEMORY_ALL_IO`
	`BUS_MEMORY-ALL-NONE`
Bus Memory Transactions -- All bus transactions from local processor	`BUS_MEMORY-ALL-SELF`	`BUS_MEMORY.ALL.SELF`	`BUS_MEMORY_ALL_SELF`
Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL) from CPU or non-CPU (all transactions).	`BUS_MEMORY-EQ_128BYTE-ANY`	`BUS_MEMORY.EQ_128BYTE.ANY`	`BUS_MEMORY_EQ_128BYTE_ANY`
Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL) from non-CPU priority agents	`BUS_MEMORY-EQ_128BYTE-IO`	`BUS_MEMORY.EQ_128BYTE.IO`	`BUS_MEMORY_EQ_128BYTE_IO`
	`BUS_MEMORY-EQ_128BYTE-NONE`
Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL) from local processor	`BUS_MEMORY-EQ_128BYTE-SELF`	`BUS_MEMORY.EQ_128BYTE.SELF`	`BUS_MEMORY_EQ_128BYTE_SELF`
Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP) CPU or non-CPU (all transactions).	`BUS_MEMORY-LT_128BYTE-ANY`	`BUS_MEMORY.LT_128BYTE.ANY`	`BUS_MEMORY_LT_128BYTE_ANY`
Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP) from non-CPU priority agents	`BUS_MEMORY-LT_128BYTE-IO`	`BUS_MEMORY.LT_128BYTE.IO`	`BUS_MEMORY_LT_128BYTE_IO`
	`BUS_MEMORY-LT_128BYTE-NONE`
Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP) local processor	`BUS_MEMORY-LT_128BYTE-SELF`	`BUS_MEMORY.LT_128BYTE.SELF`	`BUS_MEMORY_LT_128BYTE_SELF`
	`BUS_MEMORY-NONE-NONE`
Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from CPU or non-CPU (all transactions).	`BUS_MEM_READ-ALL-ANY`	`BUS_MEM_READ.ALL.ANY`	`BUS_MEM_READ_ALL_ANY`
Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from non-CPU priority agents	`BUS_MEM_READ-ALL-IO`	`BUS_MEM_READ.ALL.IO`	`BUS_MEM_READ_ALL_IO`
	`BUS_MEM_READ-ALL-NONE`
Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from local processor	`BUS_MEM_READ-ALL-SELF`	`BUS_MEM_READ.ALL.SELF`	`BUS_MEM_READ_ALL_SELF`
Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from CPU or non-CPU (all transactions).	BUS_MEM_READ-BIL-ANY	`BUS_MEM_READ.BIL.ANY`	`BUS_MEM_READ_BIL_ANY`
Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from non-CPU priority agents	`BUS_MEM_READ-BIL-IO`	`BUS_MEM_READ.BIL.IO`	`BUS_MEM_READ_BIL_IO`
	`BUS_MEM_READ-BIL-NONE`
Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from local processor	`BUS_MEM_READ-BIL-SELF`	`BUS_MEM_READ.BIL.SELF`	`BUS_MEM_READ_BIL_SELF`
Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from CPU or non-CPU (all transactions).	`BUS_MEM_READ-BRIL-ANY`	`BUS_MEM_READ.BRIL.ANY`	`BUS_MEM_READ_BRIL_ANY`
Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from non-CPU priority agents	`BUS_MEM_READ-BRIL-IO`	`BUS_MEM_READ.BRIL.IO`	`BUS_MEM_READ_BRIL_IO`
	`BUS_MEM_READ-BRIL-NONE`
Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from local processor	`BUS_MEM_READ-BRIL-SELF`	`BUS_MEM_READ.BRIL.SELF`	`BUS_MEM_READ_BRIL_SELF`
Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from CPU or non-CPU (all transactions).	`BUS_MEM_READ-BRL-ANY`	`BUS_MEM_READ.BRL.ANY`	`BUS_MEM_READ_BRL_ANY`
Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from non-CPU priority agents	`BUS_MEM_READ-BRL-IO`	`BUS_MEM_READ.BRL.IO`	`BUS_MEM_READ_BRL_IO`
	`BUS_MEM_READ-BRL-NONE`
Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from local processor	`BUS_MEM_READ-BRL-SELF`	`BUS_MEM_READ.BRL.SELF`	`BUS_MEM_READ_BRL_SELF`
Outstanding Memory Read Transactions (upper 2 bits)	`BUS_MEM_READ_OUT_HI`	`BUS_MEM_READ_OUT_HI`	`BUS_MEM_READ_OUT_HI`
Outstanding Memory Read Transactions (lower 3 bits)	`BUS_MEM_READ_OUT_LO`	`BUS_MEM_READ_OUT_LO`	`BUS_MEM_READ_OUT_LO`
Out-of-order Bus Queue Requests (upper 2 bits)	`BUS_OOQ_LIVE_REQ_HI`	`BUS_OOQ_LIVE_REQ_HI`	`BUS_OOQ_LIVE_REQ_HI`
Out-of-order Bus Queue Requests (lower 3 bits)	`BUS_OOQ_LIVE_REQ_LO`	`BUS_OOQ_LIVE_REQ_LO`	`BUS_OOQ_LIVE_REQ_LO`
Bus Read Data Transactions -- CPU or non-CPU (all transactions).	`BUS_RD_DATA-ANY`	`BUS_RD_DATA.ANY`	`BUS_RD_DATA_ANY`
Bus Read Data Transactions -- non-CPU priority agents	`BUS_RD_DATA-IO`	`BUS_RD_DATA.IO`	`BUS_RD_DATA_IO`
	`BUS_RD_DATA-NONE`
Bus Read Data Transactions -- local processor	`BUS_RD_DATA-SELF`	`BUS_RD_DATA.SELF`	`BUS_RD_DATA_SELF`
Bus Read Hit Clean Non-local Cache Transactions Bus Read Hit Modified Non-local Cache Transactions	`BUS_RD_HIT`	`BUS_RD_HIT`	`BUS_RD_HIT`
Bus Read Hit Modified Non-local Cache Transactions	`BUS_RD_HITM`	`BUS_RD_HITM`	`BUS_RD_HITM`
Bus BRIL Burst Transaction Results in HITM	`BUS_RD_INVAL_ALL_HITM`	`BUS_RD_INVAL_ALL_HITM`	`BUS_RD_INVAL_ALL_HITM`
Bus BIL Transaction Results in HITM	`BUS_RD_INVAL_HITM`	`BUS_RD_INVAL_HITM`	`BUS_RD_INVAL_HITM`
IA-32 Compatible IO Read Transactions -- CPU or non-CPU (all transactions).	`BUS_RD_IO-ANY`	`BUS_RD_IO.ANY`	`BUS_RD_IO_ANY`
IA-32 Compatible IO Read Transactions -- non-CPU priority agents	`BUS_RD_IO-IO`	`BUS_RD_IO.IO`	`BUS_RD_IO_IO`
	`BUS_RD_IO-NONE`
IA-32 Compatible IO Read Transactions -- local processor	`BUS_RD_IO-SELF`	`BUS_RD_IO.SELF`	`BUS_RD_IO_SELF`
Bus Read Partial Transactions -- CPU or non-CPU (all transactions).	`BUS_RD_PRTL-ANY`	`BUS_RD_PRTL.ANY`	`BUS_RD_PRTL_ANY`
Bus Read Partial Transactions -- non-CPU priority agents	`BUS_RD_PRTL-IO`	`BUS_RD_PRTL.IO`	`BUS_RD_PRTL_IO`
	`BUS_RD_PRTL-NONE`
Bus Read Partial Transactions -- local processor	`BUS_RD_PRTL-SELF`	`BUS_RD_PRTL.SELF`	`BUS_RD_PRTL_SELF`
Bus Snoop Queue Requests	`BUS_SNOOPQ_REQ`	`BUS_SNOOPQ_REQ`	`BUS_SNOOPQ_REQ`
Bus Snoops Total -- CPU or non-CPU (all transactions).	`BUS_SNOOPS-ANY`	`BUS_SNOOPS.ANY`	`BUS_SNOOPS_ANY`
Bus Snoops Total -- non-CPU priority agents	`BUS_SNOOPS-IO`	`BUS_SNOOPS.IO`	`BUS_SNOOPS_IO`
	`BUS_SNOOPS-NONE`
Bus Snoops Total -- local processor	`BUS_SNOOPS-SELF`	`BUS_SNOOPS.SELF`	`BUS_SNOOPS_SELF`
Bus Snoops HIT Modified Cache Line -- CPU or non-CPU (all transactions).	`BUS_SNOOPS_HITM-ANY`	`BUS_SNOOPS_HITM.ANY`	`BUS_SNOOPS_HITM_ANY`
	`BUS_SNOOPS_HITM-NONE`
Bus Snoops HIT Modified Cache Line -- local processor	`BUS_SNOOPS_HITM-SELF`	`BUS_SNOOPS_HITM.SELF`	`BUS_SNOOPS_HITM_SELF`
Bus Snoop Stall Cycles (from any agent) -- CPU or non-CPU (all transactions).	`BUS_SNOOP_STALL_ CYCLES-ANY`	`BUS_SNOOP_STALL_ CYCLES.ANY`	`BUS_SNOOP_STALL_ CYCLES_ANY`
	`BUS_SNOOP_STALL_ CYCLES-NONE`
Bus Snoop Stall Cycles (from any agent) -- local processor	`BUS_SNOOP_STALL_ CYCLES-SELF`	`BUS_SNOOP_STALL_ CYCLES.SELF`	`BUS_SNOOP_STALL_ CYCLES_SELF`
Bus Write Back Transactions -- CPU or non-CPU (all transactions).	`BUS_WR_WB-ALL-ANY`	`BUS_WR_WB.ALL.ANY`	`BUS_WR_WB_ALL_ANY`
Bus Write Back Transactions -- non-CPU priority agents	`BUS_WR_WB-ALL-IO`	`BUS_WR_WB.ALL.IO`	`BUS_WR_WB_ALL_IO`
	`BUS_WR_WB-ALL-NONE`
Bus Write Back Transactions -- local processor	`BUS_WR_WB-ALL-SELF`	`BUS_WR_WB.ALL.SELF`	`BUS_WR_WB_ALL_SELF`
Bus Write Back Transactions -- CPU or non-CPU (all transactions)/Only 0-byte transactions with write back attribute (clean cast outs) will be counted	`BUS_WR_WB-CCASTOUT-ANY`	`BUS_WR_WB.CCASTOUT.ANY`	`BUS_WR_WB_CCASTOUT_ANY`
	`BUS_WR_WB-CCASTOUT-NONE`
Bus Write Back Transactions -- local processor/Only 0-byte transactions with write back attribute (clean cast outs) will be counted	`BUS_WR_WB-CCASTOUT-SELF`	`BUS_WR_WB.CCASTOUT.SELF`	`BUS_WR_WB_CCASTOUT_SELF`
Bus Write Back Transactions -- CPU or non-CPU (all transactions)./Only cache line transactions with write back or write coalesce attributes will be counted.	`BUS_WR_WB-EQ_128BYTE-ANY`	`BUS_WR_WB.EQ_128BYTE.ANY`	`BUS_WR_WB_EQ_128BYTE_ANY`
Bus Write Back Transactions -- non-CPU priority agents/Only cache line transactions with write back or write coalesce attributes will be counted.	`BUS_WR_WB-EQ_128BYTE-IO`	`BUS_WR_WB.EQ_128BYTE.IO`	`BUS_WR_WB_EQ_128BYTE_IO`
	`BUS_WR_WB-EQ_128BYTE-NONE`
Bus Write Back Transactions -- local processor/Only cache line transactions with write back or write coalesce attributes will be counted.	`BUS_WR_WB-EQ_128BYTE-SELF`	`BUS_WR_WB.EQ_128BYTE.SELF`	`BUS_WR_WB_EQ_128BYTE_ SELF`
	`BUS_WR_WB-NONE-NONE`
Privilege Level Changes	`CPU_CPL_CHANGES`	`CPU_CPL_CHANGES`	`CPU_CPL_CHANGES`
CPU Cycles	`CPU_OP_CYCLE-ALL`	`CPU_OP_CYCLES.ALL`	`CPU_OP_CYCLES_ALL`
Fault Due to Data Debug Reg. Match to Load/Store Instruction	`DATA_DEBUG_REGISTER_FAULT`	`DATA_DEBUG_REGISTER_FAULT`	`DATA_DEBUG_REGISTER_ FAULT`
Data Debug Register Matches Data Address of Memory Reference.	`DATA_DEBUG_REGISTER_MATCHES`	`DATA_DEBUG_REGISTER_MATCHES`	`DATA_DEBUG_REGISTER_ MATCHES`
Data EAR ALAT		`DATA_EAR_EVENTS`
	`DATA_REFERENCES_SET0`	`DATA_REFERENCES_SET0`	`DATA_REFERENCES_SET0`
	`DATA_REFERENCES_SET1`	`DATA_REFERENCES_SET1`	`DATA_REFERENCES_SET1`
	`DEAR_ALAT`		`DATA_EAR_ALAT`
	`DEAR_L1DTLB_ALL`
	`DEAR_L1DTLB_FAULT`
	`DEAR_L1DTLB_TO_L2DTLB`
	`DEAR_L1DTLB_TO_VHPT`
	`DEAR_LATENCY_ANY`
Data EAR Cache -- >= 1024 Cycles	`DEAR_LATENCY_GE_1024`		`DATA_EAR_CACHE_LAT1024`
Data EAR Cache -- >= 128 Cycles	`DEAR_LATENCY_GE_128`		`DATA_EAR_CACHE_LAT128`
Data EAR Cache -- >= 16 Cycles	`DEAR_LATENCY_GE_16`		`DATA_EAR_CACHE_LAT16`
Data EAR Cache -- >= 2048 Cycles	`DEAR_LATENCY_GE_2048`		`DATA_EAR_CACHE_LAT2048`
Data EAR Cache -- >= 256 Cycles	`DEAR_LATENCY_GE_256`		`DATA_EAR_CACHE_LAT256`
Data EAR Cache -- >= 32 Cycles	`DEAR_LATENCY_GE_32`		`DATA_EAR_CACHE_LAT32`
Data EAR Cache -- >= 4 Cycles Data EAR Cache -- >= 4096 Cycles			`DATA_EAR_CACHE_LAT4`
Data EAR Cache -- >= 4096 Cycles	`DEAR_LATENCY_GE_4096`		`DATA_EAR_CACHE_LAT4096`
Data EAR Cache -- >= 512 Cycles	`DEAR_LATENCY_GE_512`		`DATA_EAR_CACHE_LAT512`
Data EAR Cache -- >= 64 Cycles	`DEAR_LATENCY_GE_64`		`DATA_EAR_CACHE_LAT64`
Data EAR Cache -- >= 8 Cycles	`DEAR_LATENCY_GE_8`		`DATA_EAR_CACHE_LAT8`
L1 Data Cache EAR Events			`DATA_EAR_EVENTS`
Data EAR TLB -- All L1 DTLB Misses			`DATA_EAR_TLB_ALL`
Data EAR TLB -- DTLB Misses which produce a software fault			`DATA_EAR_TLB_FAULT`
Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or produce a software fault Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or VHPT			`DATA_EAR_TLB_L2DTLB`
Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or produce a software fault			`DATA_EAR_TLB_L2DTLB_OR_ FAULT`
Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or VHPT			`DATA_EAR_TLB_L2DTLB_OR_ VHPT`
Data EAR TLB -- L1 DTLB Misses which hit VHPT Data EAR TLB -- L1 DTLB Misses which hit VHPT or produce a software fault			`DATA_EAR_TLB_VHPT`
Data EAR TLB -- L1 DTLB Misses which hit VHPT or produce a software fault			`DATA_EAR_TLB_VHPT_OR_ FAULT`
Data Memory References Issued to Memory Pipeline			`DATA_REFERENCES_SET0`
Data Memory References Issued to Memory Pipeline			`DATA_REFERENCES_SET0`
Number of Cycles Dispersal Stalled	`DISP_STALLED`	`DISP_STALLED`	`DISP_STALLED`
Hardware Page Walker Installs to DTLB VHPT Entries Inserted into DTLB by the Hardware Page Walker	`DTLB_INSERTS_HPW`	`DTLB_INSERTS_HPW`	`DTLB_INSERTS_HPW`
VHPT Entries Inserted into DTLB by the Hardware Page Walker	`DTLB_INSERTS_HPW_RETIRED`	`DTLB_INSERTS_HPW_RETIRED`	`DTLB_INSERTS_HPW_RETIRED`
Number of Encoded Branches Retired -- All encoded branches regardless of prediction result	`ENCBR_MISPRED_DETAIL-ALL- ALL_PRED`	`ENCBR_MISPRED_DETAIL.ALL. ALL_PRED`	`ENCBR_MISPRED_DETAIL_ALL_ ALL_PRED`
Number of Encoded Branches Retired -- All encoded branches, correctly predicted branches (outcome and target)	`ENCBR_MISPRED_DETAIL-ALL- CORRECT_PRED`	`ENCBR_MISPRED_DETAIL.ALL. CORRECT_PRED`	`ENCBR_MISPRED_DETAIL_ALL_ CORRECT_PRED`
Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong branch direction	`ENCBR_MISPRED_DETAIL-ALL- WRONG_PATH`	`ENCBR_MISPRED_DETAIL.ALL. WRONG_PATH`	`ENCBR_MISPRED_DETAIL_ALL_ WRONG_PATH`
Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong target for taken branches	`ENCBR_MISPRED_DETAIL-ALL- WRONG_TARGET`	`ENCBR_MISPRED_DETAIL.ALL. WRONG_TARGET`	`ENCBR_MISPRED_DETAIL_ALL_ WRONG_TARGET`
Number of Encoded Branches Retired -- Only non-return indirect branches, regardless of prediction result	`ENCBR_MISPRED_DETAIL-ALL2- ALL_PRED`	`ENCBR_MISPRED_DETAIL.ALL2. CORRECT_PRED`	`ENCBR_MISPRED_DETAIL_ALL2_ ALL_PRED`
Number of Encoded Branches Retired -- Only non-return indirect branches, correctly predicted branches (outcome and target)	`ENCBR_MISPRED_DETAIL-ALL2- CORRECT_PRED`	`ENCBR_MISPRED_DETAIL.ALL2. WRONG_PATH`	`ENCBR_MISPRED_DETAIL_ALL2_ CORRECT_PRED`
Number of Encoded Branches Retired -- Only non-return indirect branches, mispredicted branches due to wrong branch direction	`ENCBR_MISPRED_DETAIL-ALL2- WRONG_PATH`	`ENCBR_MISPRED_DETAIL.ALL2. WRONG_TARGET`	`ENCBR_MISPRED_DETAIL_ALL2_ WRONG_PATH`
Number of Encoded Branches Retired -- Only non-return indirect branches, mispredicted branches due to wrong target for taken branches	`ENCBR_MISPRED_DETAIL-ALL2- WRONG_TARGET`	`ENCBR_MISPRED_DETAIL.ALL2 _ALL_PRED`	`ENCBR_MISPRED_DETAIL_ALL2_ WRONG_TARGET`
Number of Encoded Branches Retired -- Only return type branches, regardless of prediction result	`ENCBR_MISPRED_DETAIL- NONE-ALL_PRED`	`ENCBR_MISPRED_DETAIL. OVERSUB.ALL_PRED`	`ENCBR_MISPRED_DETAIL_ OVERSUB_ALL_PRED`
Number of Encoded Branches Retired -- Only return type branches, correctly predicted branches (outcome and target)	`ENCBR_MISPRED_DETAIL- NONE-CORRECT_PRED`	`ENCBR_MISPRED_DETAIL. OVERSUB.CORRECT_PRED`	`ENCBR_MISPRED_DETAIL_ OVERSUB_CORRECT_PRED`
Number of Encoded Branches Retired -- Only return type branches, mispredicted branches due to wrong branch direction	`ENCBR_MISPRED_DETAIL- NONE-WRONG_PATH`	`ENCBR_MISPRED_DETAIL. OVERSUB.WRONG_PATH`	`ENCBR_MISPRED_DETAIL_ OVERSUB_WRONG_PATH`
Number of Encoded Branches Retired -- Only return type branches, mispredicted branches due to wrong target for taken branches	`ENCBR_MISPRED_DETAIL- NONE-WRONG_TARGET`	`ENCBR_MISPRED_DETAIL. OVERSUB.WRONG_TARGET`	`ENCBR_MISPRED_DETAIL_ OVERSUB_WRONG_TARGET`
	`ENCBR_MISPRED_DETAIL-OVERSUB-ALL_ PRED`
	`ENCBR_MISPRED_DETAIL-OVERSUB- CORRECT_PRED`
	`ENCBR_MISPRED_DETAIL-OVERSUB- WRONG_PATH`
	`ENCBR_MISPRED_DETAIL-OVERSUB- WRONG_TARGET`
DP Pins 0-3 Asserted -- include pin3 assertion	`EXTERN_DP_PINS_0_TO_3-ALL`		`EXTERN_DP_PINS_0_TO_3_ALL`
	`EXTERN_DP_PINS_0_TO_3-NONE`
DP Pins 0-3 Asserted -- include pin0 assertion DP Pins 0-3 Asserted -- include pin0 or pin1 assertion DP Pins 0-3 Asserted -- include pin0 or pin1 or pin2 assertion DP Pins 0-3 Asserted -- include pin0 or pin1 or pin3 assertion DP Pins 0-3 Asserted -- include pin0 or pin2 assertion DP Pins 0-3 Asserted -- include pin0 or pin2 or pin3 assertion DP Pins 0-3 Asserted -- include pin0 or pin3 assertion	`EXTERN_DP_PINS_0_TO_3-PIN0`	`EXTERN_DP_PINS_0_TO_3.PIN0`	`EXTERN_DP_PINS_0_TO_3_PIN0`
DP Pins 0-3 Asserted -- include pin0 or pin1 assertion DP Pins 0-3 Asserted -- include pin0 or pin1 or pin2 assertion DP Pins 0-3 Asserted -- include pin0 or pin1 or pin3 assertion			`EXTERN_DP_PINS_0_TO_3_PIN0_ OR_PIN1`
DP Pins 0-3 Asserted -- include pin0 or pin1 or pin2 assertion			`EXTERN_DP_PINS_0_TO_3_PIN0_ OR_PIN1_OR_PIN2`
DP Pins 0-3 Asserted -- include pin0 or pin1 or pin3 assertion			`EXTERN_DP_PINS_0_TO_3_PIN0_ OR_PIN1_OR_PIN3`
DP Pins 0-3 Asserted -- include pin0 or pin2 assertion DP Pins 0-3 Asserted -- include pin0 or pin2 or pin3 assertion			`EXTERN_DP_PINS_0_TO_3_PIN0_ OR_PIN2`
DP Pins 0-3 Asserted -- include pin0 or pin2 or pin3 assertion			`EXTERN_DP_PINS_0_TO_3_PIN0_ OR_PIN2_OR_PIN3`
DP Pins 0-3 Asserted -- include pin0 or pin3 assertion			`EXTERN_DP_PINS_0_TO_3_PIN0_ OR_PIN3`
DP Pins 0-3 Asserted -- include pin1 assertion DP Pins 0-3 Asserted -- include pin1 or pin2 assertion DP Pins 0-3 Asserted -- include pin1 or pin2 or pin3 assertion DP Pins 0-3 Asserted -- include pin1 or pin3 assertion	`EXTERN_DP_PINS_0_TO_3-PIN1`	`EXTERN_DP_PINS_0_TO_3.PIN1`	`EXTERN_DP_PINS_0_TO_3_PIN1`
DP Pins 0-3 Asserted -- include pin1 or pin2 assertion DP Pins 0-3 Asserted -- include pin1 or pin2 or pin3 assertion			`EXTERN_DP_PINS_0_TO_3_PIN1_ OR_PIN2`
DP Pins 0-3 Asserted -- include pin1 or pin2 or pin3 assertion			`EXTERN_DP_PINS_0_TO_3_PIN1_ OR_PIN2_OR_PIN3`
DP Pins 0-3 Asserted -- include pin1 or pin3 assertion			`EXTERN_DP_PINS_0_TO_3_PIN1_ OR_PIN3`
DP Pins 0-3 Asserted -- include pin2 assertion DP Pins 0-3 Asserted -- include pin2 or pin3 assertion	`EXTERN_DP_PINS_0_TO_3-PIN2`	`EXTERN_DP_PINS_0_TO_3.PIN2`	`EXTERN_DP_PINS_0_TO_3_PIN2`
DP Pins 0-3 Asserted -- include pin2 or pin3 assertion			`EXTERN_DP_PINS_0_TO_3_PIN2_ OR_PIN3`
DP Pins 0-3 Asserted -- include pin3 assertion	`EXTERN_DP_PINS_0_TO_3-PIN3`	`EXTERN_DP_PINS_0_TO_3.PIN3`	`EXTERN_DP_PINS_0_TO_3_PIN3`
DP Pins 4-5 Asserted -- include pin5 assertion	`EXTERN_DP_PINS_4_TO_5-ALL`		`EXTERN_DP_PINS_4_TO_5_ALL`
	`EXTERN_DP_PINS_4_TO_5-NONE`
DP Pins 4-5 Asserted -- include pin4 assertion	`EXTERN_DP_PINS_4_TO_5-PIN4`	`EXTERN_DP_PINS_4_TO_5.PIN4`	`EXTERN_DP_PINS_4_TO_5_PIN4`
DP Pins 4-5 Asserted -- include pin5 assertion	`EXTERN_DP_PINS_4_TO_5-PIN5`	`EXTERN_DP_PINS_4_TO_5.PIN5`	`EXTERN_DP_PINS_4_TO_5_PIN5`
Bubbles Seen by FE -- count regardless of cause Bubbles Seen by FE -- ALL except FEFLUSH and BUBBLE Bubbles Seen by FE -- ALL except IBFULl	`FE_BUBBLE-ALL`	`FE_BUBBLE.ALL`	`FE_BUBBLE_ALL`
Bubbles Seen by FE -- ALL except FEFLUSH and BUBBLE	`FE_BUBBLE-ALLBUT_FEFLUSH_ BUBBLE`	`FE_BUBBLE.ALLBUT_FEFLUSH_ BUBBLE`	`FE_BUBBLE_ALLBUT_FEFLUSH_ BUBBLE`
Bubbles Seen by FE -- ALL except IBFULl	`FE_BUBBLE-ALLBUT_IBFULL`	`FE_BUBBLE.ALLBUT_IBFULL`	`FE_BUBBLE_ALLBUT_IBFULL`
Bubbles Seen by FE -- only if caused by any of 4 branch recirculates	`FE_BUBBLE-BRANCH`	`FE_BUBBLE.BRANCH`	`FE_BUBBLE_BRANCH`
Bubbles Seen by FE -- only if caused by branch bubble stall	`FE_BUBBLE-BUBBLE`	`FE_BUBBLE.BUBBLE`	`FE_BUBBLE_BUBBLE`
Bubbles Seen by FE -- only if caused by a front-end flush	`FE_BUBBLE-FEFLUSH`	`FE_BUBBLE.FEFLUSH`	`FE_BUBBLE_FEFLUSH`
Bubbles Seen by FE -- only if caused by a recirculate for a cache line fill operation	`FE_BUBBLE-FILL_RECIRC`	`FE_BUBBLE.FILL_RECIRC`	`FE_BUBBLE_FILL_RECIRC`
Bubbles Seen by FE -- BUBBLE or BRANCH	`FE_BUBBLE-GROUP1`	`FE_BUBBLE.GROUP1`	`FE_BUBBLE_GROUP1`
Bubbles Seen by FE -- IMISS or TLBMISS	`FE_BUBBLE-GROUP2`	`FE_BUBBLE.GROUP2`	`FE_BUBBLE_GROUP2`
Bubbles Seen by FE -- FILL_RECIRC or BRANCH	`FE_BUBBLE-GROUP3`	`FE_BUBBLE.GROUP3`	`FE_BUBBLE_GROUP3`
Bubbles Seen by FE -- only if caused by instruction buffer full stall	`FE_BUBBLE-IBFULL`	`FE_BUBBLE.IBFULL`	`FE_BUBBLE_IBFULL`
Bubbles Seen by FE -- only if caused by instruction cache miss stall	`FE_BUBBLE-IMISS`	`FE_BUBBLE.IMISS`	`FE_BUBBLE_IMISS`
	`FE_BUBBLE-NONE`
Bubbles Seen by FE -- only if caused by TLB stall	`FE_BUBBLE-TLBMISS`	`FE_BUBBLE.TLBMISS`	`FE_BUBBLE_TLBMISS`
Invalid Bundles at the Entrance to IB -- count regardless of cause	`FE_LOST_BW-ALL`	`FE_LOST_BW.ALL`	`FE_LOST_BW_ALL`
Invalid Bundles at the Entrance to IB -- only if caused by branch initialization stall	`FE_LOST_BW-BI`	`FE_LOST_BW.BI`	`FE_LOST_BW_BI`
Invalid Bundles at the Entrance to IB -- only if caused by branch retirement queue stall	`FE_LOST_BW-BRQ`	`FE_LOST_BW.BRQ`	`FE_LOST_BW_BRQ`
Invalid Bundles at the Entrance to IB -- only if caused by branch interlock stall	`FE_LOST_BW-BR_ILOCK`	`FE_LOST_BW.BR_ILOCK`	`FE_LOST_BW_BR_ILOCK`
Invalid Bundles at the Entrance to IB -- only if caused by branch resteer bubble stall	`FE_LOST_BW-BUBBLE`	`FE_LOST_BW.BUBBLE`	`FE_LOST_BW_BUBBLE`
Invalid Bundles at the Entrance to IB -- only if caused by a front-end flush	`FE_LOST_BW-FEFLUSH`	`FE_LOST_BW.FEFLUSH`	`FE_LOST_BW_FEFLUSH`
Invalid Bundles at the Entrance to IB -- only if caused by a recirculate for a cache line fill operation	`FE_LOST_BW-FILL_RECIRC`	`FE_LOST_BW.FILL_RECIRC`	`FE_LOST_BW_FILL_RECIRC`
Invalid Bundles at the Entrance to IB -- only if caused by instruction buffer full stall	`FE_LOST_BW-IBFULL`	`FE_LOST_BW.IBFULL`	`FE_LOST_BW_IBFULL`
Invalid Bundles at the Entrance to IB -- only if caused by instruction cache miss stall	`FE_LOST_BW-IMISS`	`FE_LOST_BW.IMISS`	`FE_LOST_BW_IMISS`
Invalid Bundles at the Entrance to IB -- only if caused by perfect loop prediction stall	`FE_LOST_BW-PLP`	`FE_LOST_BW.PLP`	`FE_LOST_BW_PLP`
Invalid Bundles at the Entrance to IB -- only if caused by TLB stall	`FE_LOST_BW-TLBMISS`	`FE_LOST_BW.TLBMISS`	`FE_LOST_BW_TLBMISS`
Invalid Bundles at the Entrance to IB -- only if caused by unreachable bundle	`FE_LOST_BW-UNREACHED`	`FE_LOST_BW.UNREACHED`	`FE_LOST_BW_UNREACHED`
Failed fchkf	`FP_FAILED_FCHKF`	`FP_FAILED_FCHKF`	`FP_FAILED_FCHKF`
SIR Stall Without a Trap	`FP_FALSE_SIRSTALL`	`FP_FALSE_SIRSTALL`	`FP_FALSE_SIRSTALL`
FP Result Flushed to Zero	`FP_FLUSH_TO_ZERO`	`FP_FLUSH_TO_ZERO`	`FP_FLUSH_TO_ZERO`
Retired FP Operations	`FP_OPS_RETIRED`	`FP_OPS_RETIRED`	`FP_OPS_RETIRED`
SIR stall asserted and leads to a trap	`FP_TRUE_SIRSTALL`	`FP_TRUE_SIRSTALL`	`FP_TRUE_SIRSTALL`
Data Memory References to VHPT	`HPW_DATA_REFERENCES`	`HPW_DATA_REFERENCES`	`HPW_DATA_REFERENCES`
IA-32 Instructions Retired	`IA32_INST_RETIRED`	`IA32_INST_RETIRED`	`IA32_INST_RETIRED`
IA-64 to/from IA-32 ISA Transitions	`IA32_ISA_TRANSITIONS`	`IA32_ISA_TRANSITIONS`	`IA32_ISA_TRANSITIONS`
Retired IA-64 Instructions, alias to IA64_INST_RETIRED_THIS Retired IA-64 Instructions -- Retired IA-64 Instructions			`IA64_INST_RETIRED`
Retired IA-64 Instructions -- Retired IA-64 Instructions	`IA64_INST_RETIRED-THIS`	`IA64_INST_RETIRED.THIS`	`IA64_INST_RETIRED_THIS`
Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 0 and opcode matcher PMC8. Code executed with PSR.is=1 is included.	`IA64_TAGGED_INST_ RETIRED-IBRP0_PMC8`	`IA64_TAGGED_INST_ RETIRED.IBRP0_PMC8`	`IA64_TAGGED_INST_RETIRED_ IBRP0_PMC8`
Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 1 and opcode matcher PMC9. Code executed with PSR.is=1 is included.	`IA64_TAGGED_INST_RETIRED- IBRP1_PMC9`	`IA64_TAGGED_INST_RETIRED. IBRP1_PMC9`	`IA64_TAGGED_INST_RETIRED_ IBRP1_PMC9`
Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 2 and opcode matcher PMC8. Code executed with PSR.is=1 is not included.	`IA64_TAGGED_INST_ RETIRED-IBRP2_PMC8`	`IA64_TAGGED_INST_ RETIRED.IBRP2_PMC8`	`IA64_TAGGED_INST_ RETIRED_IBRP2_PMC8`
Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 3 and opcode matcher PMC9. Code executed with PSR.is=1 is not included.	`IA64_TAGGED_INST_ RETIRED-IBRP3_PMC9`	`IA64_TAGGED_INST_ RETIRED.IBRP3_PMC9`	`IA64_TAGGED_INST_ RETIRED_IBRP3_PMC9`
Invalid Bundles at the Exit from IB -- count regardless of cause	`IDEAL_BE_LOST_BW_DUE_TO_ FE-ALL`	`IDEAL_BE_LOST_BW_DUE_TO_ FE.ALL`	`IDEAL_BE_LOST_BW_DUE_TO_ FE_ALL`
Invalid Bundles at the Exit from IB -- only if caused by branch initialization stall	`IDEAL_BE_LOST_BW_DUE_TO_ FE-BI`	`IDEAL_BE_LOST_BW_DUE_TO_ FE.BI`	`IDEAL_BE_LOST_BW_DUE_TO_ FE_BI`
Invalid Bundles at the Exit from IB -- only if caused by branch retirement queue stall	`IDEAL_BE_LOST_BW_DUE_TO_ FE-BRQ`	`IDEAL_BE_LOST_BW_DUE_TO_ FE.BRQ`	`IDEAL_BE_LOST_BW_DUE_TO_ FE_BRQ`
Invalid Bundles at the Exit from IB -- only if caused by branch interlock stall	`IDEAL_BE_LOST_BW_DUE_TO_ FE-BR_ILOCK`	`IDEAL_BE_LOST_BW_DUE_TO_ FE.BR_ILOCK`	`IDEAL_BE_LOST_BW_DUE_TO_ FE_BR_ILOCK`
Invalid Bundles at the Exit from IB -- only if caused by branch resteer bubble stall	`IDEAL_BE_LOST_BW_DUE_TO_ FE-BUBBLE`	`IDEAL_BE_LOST_BW_DUE_TO_ FE.BUBBLE`	`IDEAL_BE_LOST_BW_DUE_TO_ FE_BUBBLE`
Invalid Bundles at the Exit from IB -- only if caused by a front-end flush	`IDEAL_BE_LOST_BW_DUE_TO_ FE-FEFLUSH`	`IDEAL_BE_LOST_BW_DUE_ TO_FE.FEFLUSH`	`IDEAL_BE_LOST_BW_DUE_TO_ FE_FEFLUSH`
Invalid Bundles at the Exit from IB -- only if caused by a recirculate for a cache line fill operation	`IDEAL_BE_LOST_BW_DUE_TO_ FE-FILL_RECIRC`	`IDEAL_BE_LOST_BW_DUE_TO_ FE.FILL_RECIRC`	`IDEAL_BE_LOST_BW_DUE_TO_ FE_FILL_RECIRC`
Invalid Bundles at the Exit from IB -- (* meaningless for this event *)	`IDEAL_BE_LOST_BW_DUE_TO_ FE-IBFULL`	`IDEAL_BE_LOST_BW_DUE_TO_ FE.IBFULL`	`IDEAL_BE_LOST_BW_DUE_TO_ FE_IBFULL`
Invalid Bundles at the Exit from IB -- only if caused by instruction cache miss stall	`IDEAL_BE_LOST_BW_DUE_TO_ FE-IMISS`	`IDEAL_BE_LOST_BW_DUE_TO_ FE.IMISS`	`IDEAL_BE_LOST_BW_DUE_TO_ FE_IMISS`
Invalid Bundles at the Exit from IB -- only if caused by perfect loop prediction stall	`IDEAL_BE_LOST_BW_DUE_TO_ FE-PLP`	`IDEAL_BE_LOST_BW_DUE_TO_ FE.PLP`	`IDEAL_BE_LOST_BW_DUE_TO_ FE_PLP`
Invalid Bundles at the Exit from IB -- only if caused by TLB stall	`IDEAL_BE_LOST_BW_DUE_TO_ FE-TLBMISS`	`IDEAL_BE_LOST_BW_DUE_TO_ FE.TLBMISS`	`IDEAL_BE_LOST_BW_DUE_TO_ FE_TLBMISS`
Invalid Bundles at the Exit from IB -- only if caused by unreachable bundle	`IDEAL_BE_LOST_BW_DUE_TO_ FE-UNREACHED`	`IDEAL_BE_LOST_BW_DUE_TO_ FE.UNREACHED`	`IDEAL_BE_LOST_BW_DUE_TO_ FE_UNREACHED`
	`IEAR_ALL_RAB`
	`IEAR_L1ITLB_ALL`
	`IEAR_L1ITLB_FAULT`
	`IEAR_L1ITLB_TO_L2ITLB`
	`IEAR_L1ITLB_TO_VHPT`
	`IEAR_LATENCY_ALL`
	`IEAR_LATENCY_GE_1024`
	`IEAR_LATENCY_GE_128`
	`IEAR_LATENCY_GE_16`
	`IEAR_LATENCY_GE_256`
	`IEAR_LATENCY_GE_32`
	`IEAR_LATENCY_GE_4`
	`IEAR_LATENCY_GE_4096`
	`IEAR_LATENCY_GE_8`
Retired chk.a and ld.c Instructions -- both integer and floating point instructions	`INST_CHKA_LDC_ALAT-ALL`	`INST_CHKA_LDC_ALAT.ALL`	`INST_CHKA_LDC_ALAT_ALL`
Retired chk.a and ld.c Instructions -- only floating point instructions	`INST_CHKA_LDC_ALAT-FP`	`INST_CHKA_LDC_ALAT.FP`	`INST_CHKA_LDC_ALAT_FP`
Retired chk.a and ld.c Instructions -- only integer instructions	`INST_CHKA_LDC_ALAT-INT`	`INST_CHKA_LDC_ALAT.INT`	`INST_CHKA_LDC_ALAT_INT`
	`INST_CHKA_LDC_ALAT-NONE`
Syllables Dispersed from REN to REG stage	`INST_DISPERSED`	`INST_DISPERSED`	`INST_DISPERSED`
Failed chk.a and ld.c Instructions -- both integer and floating point instructions	`INST_FAILED_CHKA_LDC_ ALAT-ALL`	`INST_FAILED_CHKA_LDC_ ALAT.ALL`	`INST_FAILED_CHKA_LDC_ ALAT_ALL`
Failed chk.a and ld.c Instructions -- only floating point instructions	`INST_FAILED_CHKA_LDC_ ALAT-FP`	`INST_FAILED_CHKA_LDC_ ALAT.FP`	`INST_FAILED_CHKA_LDC_ ALAT_FP`
Failed chk.a and ld.c Instructions -- only integer instructions	`INST_FAILED_CHKA_LDC_ ALAT-INT`	`INST_FAILED_CHKA_LDC_ ALAT.INT`	`INST_FAILED_CHKA_LDC_ ALAT_INT`
	`INST_FAILED_CHKA_LDC_ ALAT-NONE`
Failed chk.s Instructions -- both integer and floating point instructions	`INST_FAILED_CHKS_ RETIRED-ALL`	`INST_FAILED_CHKS_ RETIRED.ALL`	`INST_FAILED_CHKS_ RETIRED_ALL`
Failed chk.s Instructions -- only floating point instructions	`INST_FAILED_CHKS_ RETIRED-FP`	`INST_FAILED_CHKS_ RETIRED.FP`	`INST_FAILED_CHKS_ RETIRED_FP`
Failed chk.s Instructions -- only integer instructions	`INST_FAILED_CHKS_ RETIRED-INT`	`INST_FAILED_CHKS_RETIRED.INT`	`INST_FAILED_CHKS_ RETIRED_INT`
	`INST_FAILED_CHKS_ RETIRED-NONE`
Bundle Pairs Written from L2 into FE	`ISB_BUNPAIRS_IN`	`ISB_BUNPAIRS_IN`	`ISB_BUNPAIRS_IN`
ITLB Misses Demand Fetch -- All tlb misses will be counted. Note that this is not equal to sum of the L1ITLB and L2ITLB umasks because any access could be a miss in L1ITLB and L2ITLB.	`ITLB_MISSES_FETCH-ALL`	`ITLB_MISSES_FETCH.ALL`	`ITLB_MISSES_FETCH_ALL`
ITLB Misses Demand Fetch -- All misses in L1ITLB will be counted. even if L1ITLB is not updated for an access (Uncacheable/nat page/not present page/faulting/some flushed), it will be counted here.	`ITLB_MISSES_FETCH-L1ITLB`	`ITLB_MISSES_FETCH.L1ITLB`	`ITLB_MISSES_FETCH_L1ITLB`
ITLB Misses Demand Fetch -- All misses in L1ITLB which also missed in L2ITLB will be counted.	`ITLB_MISSES_FETCH-L2ITLB`	`ITLB_MISSES_FETCH.L2ITLB`	`ITLB_MISSES_FETCH_L2ITLB`
	`ITLB_MISSES_FETCH-NONE`
L1DTLB Misses That Hit in the L2DTLB for Accesses Counted in L1D_READS	`L1DTLB_TRANSFER`	`L1DTLB_TRANSFER`	`L1DTLB_TRANSFER`
L1 Data Cache Reads	`L1D_READS_SET0`	`L1D_READS_SET0`	`L1D_READS_SET0`
L1 Data Cache Reads	`L1D_READS_SET1`	`L1D_READS_SET1`	`L1D_READS_SET1`
L1 Data Cache Read Misses -- all L1D read misses will be counted.	`L1D_READ_MISSES-ALL`	`L1D_READ_MISSES.ALL`	`L1D_READ_MISSES_ALL`
L1 Data Cache Read Misses -- only L1D read misses caused by RSE fills will be counted	`L1D_READ_MISSES-RSE_FILL`	`L1D_READ_MISSES.RSE_FILL`	`L1D_READ_MISSES_RSE_FILL`
L1ITLB Hardware Page Walker Inserts	`L1ITLB_INSERTS_HPW`	`L1ITLB_INSERTS_HPW`	`L1ITLB_INSERTS_HPW`
L1I EAR Cache -- > 0 Cycles (All L1 Misses)			`L1I_EAR_CACHE_LAT0`
L1I EAR Cache -- >= 1024 Cycles			`L1I_EAR_CACHE_LAT1024`
L1I EAR Cache -- >= 128 Cycles			`L1I_EAR_CACHE_LAT128`
L1I EAR Cache -- >= 16 Cycles			`L1I_EAR_CACHE_LAT16`
L1I EAR Cache -- >= 256 Cycles			`L1I_EAR_CACHE_LAT256`
L1I EAR Cache -- >= 32 Cycles			`L1I_EAR_CACHE_LAT32`
L1I EAR Cache -- >= 4 Cycles L1I EAR Cache -- >= 4096 Cycles			`L1I_EAR_CACHE_LAT4`
L1I EAR Cache -- >= 4096 Cycles			`L1I_EAR_CACHE_LAT4096`
L1I EAR Cache -- >= 8 Cycles			`L1I_EAR_CACHE_LAT8`
L1I EAR Cache -- RAB HIT			`L1I_EAR_CACHE_RAB`
Instruction EAR Events		`L1I_EAR_EVENTS`	`L1I_EAR_EVENTS`
L1I EAR TLB -- All L1 ITLB Misses			`L1I_EAR_TLB_ALL`
L1I EAR TLB -- ITLB Misses which produced a fault			`L1I_EAR_TLB_FAULT`
L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or produce a software fault L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or VHPT			`L1I_EAR_TLB_L2TLB`
L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or produce a software fault			`L1I_EAR_TLB_L2TLB_OR_FAULT`
L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or VHPT			`L1I_EAR_TLB_L2TLB_OR_VHPT`
L1I EAR TLB -- L1 ITLB Misses which hit VHPT L1I EAR TLB -- L1 ITLB Misses which hit VHPT or produce a software fault			`L1I_EAR_TLB_VHPT`
L1I EAR TLB -- L1 ITLB Misses which hit VHPT or produce a software fault			`L1I_EAR_TLB_VHPT_OR_FAULT`
"Just-In-Time" Instruction Fetch Hitting in and Being Bypassed from ISB	`L1I_FETCH_ISB_HIT`	`L1I_FETCH_ISB_HIT`	`L1I_FETCH_ISB_HIT`
Instruction Fetch Hitting in RAB	`L1I_FETCH_RAB_HIT`	`L1I_FETCH_RAB_HIT`	`L1I_FETCH_RAB_HIT`
L1 Instruction Cache Fills	`L1I_FILLS`	`L1I_FILLS`	`L1I_FILLS`
L1 Instruction Prefetch Requests	`L1I_PREFETCHES`	`L1I_PREFETCHES`	`L1I_PREFETCHES`
Prefetch Pipeline Stalls -- Number of clocks prefetch pipeline is stalled	`L1I_PREFETCH_STALL-ALL`	`L1I_PREFETCH_STALL.ALL`	`L1I_PREFETCH_STALL_ALL`
Prefetch Pipeline Stalls -- Number of clocks flow is not asserted	`L1I_PREFETCH_STALL-FLOW`	`L1I_PREFETCH_STALL.FLOW`	`L1I_PREFETCH_STALL_FLOW`
	`L1I_PREFETCH_STALL-NONE`
L1ITLB Purges Handled by L1I	`L1I_PURGE`	`L1I_PURGE`	`L1I_PURGE`
PVAB Overflow	`L1I_PVAB_OVERFLOW`	`L1I_PVAB_OVERFLOW`	`L1I_PVAB_OVERFLOW`
Is RAB Almost Full?	`L1I_RAB_ALMOST_FULL`	`L1I_RAB_ALMOST_FULL`	`L1I_RAB_ALMOST_FULL`
Is RAB Full?	`L1I_RAB_FULL`	`L1I_RAB_FULL`	`L1I_RAB_FULL`
L1 Instruction Cache Reads	`L1I_READS`	`L1I_READS`	`L1I_READS`
Snoop Requests Handled by L1I	`L1I_SNOOP`	`L1I_SNOOP`	`L1I_SNOOP`
L1 Instruction Cache Line Prefetch Requests	`L1I_STRM_PREFETCHES`	`L1I_STRM_PREFETCHES`	`L1I_STRM_PREFETCHES`
L2DTLB Misses	`L2DTLB_MISSES`	`L2DTLB_MISSES`	`L2DTLB_MISSES`
Valid Line Replaced When Invalid Line Is Available -- Valid line replaced when invalid line is available	`L2_BAD_LINES_SELECTED-ANY`	`L2_BAD_LINES_SELECTED.ANY`	`L2_BAD_LINES_SELECTED_ANY`
Count L2 Bypasses -- Count only L2 data bypasses (L1D to L2A)	`L2_BYPASS-L2_DATA1`	`L2_BYPASS.L2_DATA1`	`L2_BYPASS_L2_DATA1`
Count L2 Bypasses -- Count only L2 data bypasses (L1W to L2I)	`L2_BYPASS-L2_DATA2`	`L2_BYPASS.L2_DATA2`	`L2_BYPASS_L2_DATA2`
Count L2 Bypasses -- Count only L2 instruction bypasses (L1D to L2A)	`L2_BYPASS-L2_INST1`	`L2_BYPASS.L2_INST1`	`L2_BYPASS_L2_INST1`
Count L2 Bypasses -- Count only L2 instruction bypasses (L1W to L2I)	`L2_BYPASS-L2_INST2`	`L2_BYPASS.L2_INST2`	`L2_BYPASS_L2_INST2`
Count L2 Bypasses -- Count only L3 data bypasses (L1D to L2A)	`L2_BYPASS-L3_DATA1`	`L2_BYPASS.L3_DATA1`	`L2_BYPASS_L3_DATA1`
Count L2 Bypasses -- Count only L3 instruction bypasses (L1D to L2A)	`L2_BYPASS-L3_INST1`	`L2_BYPASS.L3_INST1`	`L2_BYPASS_L3_INST1`
	`L2_BYPASS-NONE1`
	`L2_BYPASS-NONE2`
Data Read/Write Access to L2 -- count both read and write operations (semaphores will count as 2)	`L2_DATA_REFERENCES-L2_ALL`	`L2_DATA_REFERENCES.L2_ALL`	`L2_DATA_REFERENCES_L2_ALL`
Data Read/Write Access to L2 -- count only data read and semaphore operations.	`L2_DATA_REFERENCES-L2_ DATA_READS`	`L2_DATA_REFERENCES.L2_ DATA_READS`	`L2_DATA_REFERENCES_L2_ DATA_READS`
Data Read/Write Access to L2 -- count only data write and semaphore operations	`L2_DATA_REFERENCES-L2_ DATA_WRITES`	`L2_DATA_REFERENCES.L2_ DATA_WRITES`	`L2_DATA_REFERENCES_L2_ DATA_WRITES`
	`L2_DATA_REFERENCES-NONE`
L2D Fill Buffer Is Full -- L2 Fill buffer is full	`L2_FILLB_FULL-THIS`	`L2_FILLB_FULL.THIS`	`L2_FILLB_FULL_THIS`
Forced Recirculates -- count forced recirculates regardless of cause. SMC_HIT, TRAN_PREF & SNP_OR_L3 will not be included here.	`L2_FORCE_RECIRC-ANY`	`L2_FORCE_RECIRC.ANY`	`L2_FORCE_RECIRC_ANY`
Forced Recirculates -- count only those caused by an L2 miss which hit in the fill buffer.	`L2_FORCE_RECIRC-FILL_HIT`	`L2_FORCE_RECIRC.FILL_HIT`	`L2_FORCE_RECIRC_FILL_HIT`
Forced Recirculates -- caused by an L2 miss when a force recirculate already existed	`L2_FORCE_RECIRC-FRC_RECIRC`	`L2_FORCE_RECIRC.FRC_RECIRC`	`L2_FORCE_RECIRC_FRC_RECIRC`
Forced Recirculates -- caused by L2 miss when instruction prefetch buffer miss already existed	`L2_FORCE_RECIRC-IPF_MISS`	`L2_FORCE_RECIRC.IPF_MISS`	`L2_FORCE_RECIRC_IPF_MISS`
Forced Recirculates -- count only those caused by forced limbo	`L2_FORCE_RECIRC-L1W`	`L2_FORCE_RECIRC.L1W`	`L2_FORCE_RECIRC_L1W`
	`L2_FORCE_RECIRC-NONE1`
	`L2_FORCE_RECIRC-NONE2`
	`L2_FORCE_RECIRC-NONE3`
Forced Recirculates -- caused by an L2 miss when an OZQ miss already existed	`L2_FORCE_RECIRC-OZQ_MISS`	`L2_FORCE_RECIRC.OZQ_MISS`	`L2_FORCE_RECIRC_OZQ_MISS`
Forced Recirculates -- caused by an L2 miss when a miss to the same index already existed	`L2_FORCE_RECIRC-SAME_INDEX`	`L2_FORCE_RECIRC.SAME_INDEX`	`L2_FORCE_RECIRC_SAME_INDEX`
Forced Recirculates -- count only those caused by SMC hits due to an ifetch and load to same cache line or a pending WT store	`L2_FORCE_RECIRC-SMC_HIT`	`L2_FORCE_RECIRC.SMC_HIT`	`L2_FORCE_RECIRC_SMC_HIT`
Forced Recirculates -- count only those caused by a snoop or L3 issue	`L2_FORCE_RECIRC-SNP_OR_L3`	`L2_FORCE_RECIRC.SNP_OR_L3`	`L2_FORCE_RECIRC_SNP_OR_L3`
Forced Recirculates -- count only those caused by L2 hits caused by in flight snoops, stores with a sibling miss to the same index, sibling probe to the same line or pending sync.ia instructions.	`L2_FORCE_RECIRC-TAG_NOTOK`	`L2_FORCE_RECIRC.TAG_NOTOK`	`L2_FORCE_RECIRC_TAG_NOTOK`
Forced Recirculates -- count only those caused by transforms to prefetches	`L2_FORCE_RECIRC-TRAN_PREF`	`L2_FORCE_RECIRC.TRAN_PREF`	`L2_FORCE_RECIRC_TRAN_PREF`
Forced Recirculates -- count only those caused by an L2 miss with victim buffer full	`L2_FORCE_RECIRC-VIC_BUF_FULL`	`L2_FORCE_RECIRC.VIC_BUF_FULL`	`L2_FORCE_RECIRC_VIC_BUF_FULL`
Forced Recirculates -- count only those caused by an L2 miss with pending victim	`L2_FORCE_RECIRC-VIC_PEND`	`L2_FORCE_RECIRC.VIC_PEND`	`L2_FORCE_RECIRC_VIC_PEND`
Instruction Fetch Recirculates Received by L2D -- Instruction fetch recirculates received by L2	`L2_GOT_RECIRC_IFETCH-ANY`	`L2_GOT_RECIRC_IFETCH.ANY`	`L2_GOT_RECIRC_IFETCH_ANY`
Counts Number of OZQ Accesses Recirculated to L1D	`L2_GOT_RECIRC_OZQ_ACC`	`L2_GOT_RECIRC_OZQ_ACC`	`L2_GOT_RECIRC_OZQ_ACC`
Instruction Fetch Cancels by the L2 -- total instruction fetch cancels by L2	`L2_IFET_CANCELS-ANY`	`L2_IFET_CANCELS.ANY`	`L2_IFET_CANCELS_ANY`
Instruction Fetch Cancels by the L2 -- ifetch cancels due to bypassing	`L2_IFET_CANCELS-BYPASS`	`L2_IFET_CANCELS.BYPASS`	`L2_IFET_CANCELS_BYPASS`
Instruction Fetch Cancels by the L2 -- ifetch cancels due to change priority	`L2_IFET_CANCELS-CHG_PRIO`	`L2_IFET_CANCELS.CHG_PRIO`	`L2_IFET_CANCELS_CHG_PRIO`
Instruction Fetch Cancels by the L2 -- ifetch/prefetch cancels due to a data read	`L2_IFET_CANCELS-DATA_RD`	`L2_IFET_CANCELS.DATA_RD`	`L2_IFET_CANCELS_DATA_RD`
Instruction Fetch Cancels by the L2 -- ifetch cancels because it did not recirculate	`L2_IFET_CANCELS-DIDNT_RECIR`	`L2_IFET_CANCELS.DIDNT_RECIR`	`L2_IFET_CANCELS_DIDNT_RECIR`
Instruction Fetch Cancels by the L2 -- due to ifetch bypass during last clock	`L2_IFET_CANCELS-IFETCH_BYP`	`L2_IFET_CANCELS.IFETCH_BYP`	`L2_IFET_CANCELS_IFETCH_BYP`
	`L2_IFET_CANCELS-NONE`
Instruction Fetch Cancels by the L2 -- ifetch cancels due to preempts	`L2_IFET_CANCELS-PREEMPT`	`L2_IFET_CANCELS.PREEMPT`	`L2_IFET_CANCELS_PREEMPT`
Instruction Fetch Cancels by the L2 -- ifetch cancels because of recirculate oversubscription	`L2_IFET_CANCELS-RECIR_ OVER_SUB`	`L2_IFET_CANCELS.RECIR_ OVER_SUB`	`L2_IFET_CANCELS_RECIR_ OVER_SUB`
Instruction Fetch Cancels by the L2 -- ifetch cancels due to a store or fill or write back	`L2_IFET_CANCELS-ST_FILL_WB`	`L2_IFET_CANCELS.ST_FILL_WB`	`L2_IFET_CANCELS_ST_FILL_WB`
L2 Instruction Demand Fetch Requests	`L2_INST_DEMAND_READS`	`L2_INST_DEMAND_READS`	`L2_INST_DEMAND_READS`
L2 Instruction Prefetch Requests	`L2_INST_PREFETCHES`	`L2_INST_PREFETCHES`	`L2_INST_PREFETCHES`
Instruction Fetch Recirculates Issued by L2 -- Instruction fetch recirculates issued by L2	`L2_ISSUED_RECIRC_IFETCH-ANY`	`L2_ISSUED_RECIRC_IFETCH.ANY`	`L2_ISSUED_RECIRC_IFETCH_ANY`
Count Number of Times a Recirculate Issue Was Attempted and Not Preempted	`L2_ISSUED_RECIRC_OZQ_ACC`	`L2_ISSUED_RECIRC_OZQ_ACC`	`L2_ISSUED_RECIRC_OZQ_ACC`
Canceled L3 Accesses -- count cancels due to any reason. This umask will count more than the sum of all the other umasks. It will count things that weren't committed accesses when they reached L1w, but the L2 attempted to bypass them to the L3 anyway (speculatively). This will include accesses made repeatedly while the main pipeline is stalled and the L1d is attempting to recirculate an access down the L1d pipeline. Thus, an access could get counted many times before it really does get bypassed to the L3. It is a measure of how many times we asserted a request to the L3 but didn't confirm it.	`L2_L3ACCESS_CANCEL-ANY`	`L2_L3ACCESS_CANCEL.ANY`	`L2_L3ACCESS_CANCEL_ANY`
Canceled L3 Accesses -- data fetches	`L2_L3ACCESS_CANCEL-DFETCH`	`L2_L3ACCESS_CANCEL.DFETCH`	`L2_L3ACCESS_CANCEL_DFETCH`
Canceled L3 Accesses -- ebl rejects	`L2_L3ACCESS_CANCEL- EBL_REJECT`	`L2_L3ACCESS_CANCEL. EBL_REJECT`	`L2_L3ACCESS_CANCEL_ EBL_REJECT`
Canceled L3 Accesses -- filld being full	`L2_L3ACCESS_CANCEL- FILLD_FULL`	`L2_L3ACCESS_CANCEL. FILLD_FULL`	`L2_L3ACCESS_CANCEL_ FILLD_FULL`
Canceled L3 Accesses -- instruction fetches	`L2_L3ACCESS_CANCEL- IFETCH`	`L2_L3ACCESS_CANCEL. IFETCH`	`L2_L3ACCESS_CANCEL_ IFETCH`
Canceled L3 Accesses -- invalid L3 bypasses	`L2_L3ACCESS_CANCEL- INV_L3_BYP`	`L2_L3ACCESS_CANCEL. INV_L3_BYP`	`L2_L3ACCESS_CANCEL_ INV_L3_BYP`
	`L2_L3ACCESS_CANCEL-NONE`
	`L2_L3ACCESS_CANCEL-NONE1`
	`L2_L3ACCESS_CANCEL-NONE2`
Canceled L3 Accesses -- speculative L3 bypasses	`L2_L3ACCESS_CANCEL- SPEC_L3_BYP`	`L2_L3ACCESS_CANCEL. SPEC_L3_BYP`	`L2_L3ACCESS_CANCEL_ SPEC_L3_BYP`
Canceled L3 Accesses -- Uncacheable blocked L3 Accesses	`L2_L3ACCESS_CANCEL- UC_BLOCKED`	`L2_L3ACCESS_CANCEL. UC_BLOCKED`	`L2_L3ACCESS_CANCEL_ UC_BLOCKED`
L2 Misses	`L2_MISSES`	`L2_MISSES`	`L2_MISSES`
Different Operations Issued by L2D -- Count only valid floating point loads	`L2_OPS_ISSUED-FP_LOAD`	`L2_OPS_ISSUED.FP_LOAD`	`L2_OPS_ISSUED_FP_LOAD`
Different Operations Issued by L2D -- Count only valid integer loads	`L2_OPS_ISSUED-INT_LOAD`	`L2_OPS_ISSUED.INT_LOAD`	`L2_OPS_ISSUED_INT_LOAD`
	`L2_OPS_ISSUED-NONE`
Different Operations Issued by L2D -- Count only valid non-load, no-store accesses	`L2_OPS_ISSUED-NST_NLD`	`L2_OPS_ISSUED.NST_NLD`	`L2_OPS_ISSUED_NST_NLD`
Different Operations Issued by L2D -- Count only valid read_modify_write stores	`L2_OPS_ISSUED-RMW`	`L2_OPS_ISSUED.RMW`	`L2_OPS_ISSUED_RMW`
Different Operations Issued by L2D -- Count only valid non-read_modify_write stores	`L2_OPS_ISSUED-STORE`	`L2_OPS_ISSUED.STORE`	`L2_OPS_ISSUED_STORE`
L2 OZ Data Buffer Is Full -- L2 OZ Data Buffer is full	`L2_OZDB_FULL-THIS`	`L2_OZDB_FULL.THIS`	`L2_OZDB_FULL_THIS`
Clocks With Acquire Ordering Attribute Existed in L2 OZQ	`L2_OZQ_ACQUIRE`	`L2_OZQ_ACQUIRE`	`L2_OZQ_ACQUIRE`
L2 OZQ Cancels (Late or Any) -- counts the total OZ Queue cancels	`L2_OZQ_CANCELS0-ANY`	`L2_OZQ_CANCELS0.ANY`	`L2_OZQ_CANCELS0_ ANY`
L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by acquires	`L2_OZQ_CANCELS0- LATE_ACQUIRE`	`L2_OZQ_CANCELS0. LATE_ACQUIRE`	`L2_OZQ_CANCELS0_ LATE_ACQUIRE`
L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by L1D to L2A bypass effective releases	`L2_OZQ_CANCELS0- LATE_BYP_EFFRELEASE`	`L2_OZQ_CANCELS0. LATE_BYP_EFFRELEASE`	`L2_OZQ_CANCELS0_ LATE_BYP_EFFRELEASE`
L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by releases	`L2_OZQ_CANCELS0- LATE_RELEASE`	`L2_OZQ_CANCELS0. LATE_RELEASE`	`L2_OZQ_CANCELS0_ LATE_RELEASE`
L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by speculative bypasses	`L2_OZQ_CANCELS0- LATE_SPEC_BYP`	`L2_OZQ_CANCELS0. LATE_SPEC_BYP`	`L2_OZQ_CANCELS0_LATE_ SPEC_BYP`
L2 OZQ Cancels (Specific Reason Set 1) -- bank conflicts	`L2_OZQ_CANCELS0-NONE`
L2 OZQ Cancels (Specific Reason Set 1) -- caused by a canceled store in L2M	`L2_OZQ_CANCELS1-BANK_CONF`	`L2_OZQ_CANCELS1.BANK_CONF`	`L2_OZQ_CANCELS1_BANK_CONF`
L2 OZQ Cancels (Specific Reason Set 1) -- a ccv	`L2_OZQ_CANCELS1-CANC_L2M_ST`	`L2_OZQ_CANCELS1.CANC_L2M_ST`	`L2_OZQ_CANCELS1_CANC_L2M_ST`
L2 OZQ Cancels (Specific Reason Set 1) -- ECC hardware detecting a problem	`L2_OZQ_CANCELS1-CCV`	`L2_OZQ_CANCELS1.CCV`	`L2_OZQ_CANCELS1_CCV`
L2 OZQ Cancels (Specific Reason Set 1) -- a ifetch conflict (canceling HPW?)	`L2_OZQ_CANCELS1-ECC`	`L2_OZQ_CANCELS1.ECC`	`L2_OZQ_CANCELS1_ECC`
L2 OZQ Cancels (Specific Reason Set 1) -- L1D fill in L2M	`L2_OZQ_CANCELS1-HPW_ IFETCH_CONF`	`L2_OZQ_CANCELS1.HPW_ IFETCH_CONF`	`L2_OZQ_CANCELS1_HPW_ IFETCH_CONF`
L2 OZQ Cancels (Specific Reason Set 1) -- an L1 fill conflict	`L2_OZQ_CANCELS1-L1DF_L2M`	`L2_OZQ_CANCELS1.L1DF_L2M`	`L2_OZQ_CANCELS1_L1DF_L2M`
L2 OZQ Cancels (Specific Reason Set 1) -- a store match in L2A	`L2_OZQ_CANCELS1-L1_FILL_CONF`	`L2_OZQ_CANCELS1.L1_FILL_CONF`	`L2_OZQ_CANCELS1_L1_FILL_CONF`
L2 OZQ Cancels (Specific Reason Set 1) -- a store match in L2D	`L2_OZQ_CANCELS1-L2A_ST_MAT`	`L2_OZQ_CANCELS1.L2A_ST_MAT`	`L2_OZQ_CANCELS1_L2A_ST_MAT`
L2 OZQ Cancels (Specific Reason Set 1) -- a store match in L2M	`L2_OZQ_CANCELS1-L2D_ST_MAT`	`L2_OZQ_CANCELS1.L2D_ST_MAT`	`L2_OZQ_CANCELS1_L2D_ST_MAT`
L2 OZQ Cancels (Specific Reason Set 1) -- a memory fence instruction	`L2_OZQ_CANCELS1-L2M_ST_MAT`	`L2_OZQ_CANCELS1.L2M_ST_MAT`	`L2_OZQ_CANCELS1_L2M_ST_MAT`
L2 OZQ Cancels (Specific Reason Set 1) -- caused by release	`L2_OZQ_CANCELS1-MFA`	`L2_OZQ_CANCELS1.MFA`	`L2_OZQ_CANCELS1_MFA`
L2 OZQ Cancels (Specific Reason Set 1) -- a semaphore	`L2_OZQ_CANCELS1-NONE`
L2 OZQ Cancels (Specific Reason Set 1) -- a store fill conflict	`L2_OZQ_CANCELS1-REL`	`L2_OZQ_CANCELS1.REL`	`L2_OZQ_CANCELS1_REL`
L2 OZQ Cancels (Specific Reason Set 1) -- caused by sync.i	`L2_OZQ_CANCELS1-SEM`	`L2_OZQ_CANCELS1.SEM`	`L2_OZQ_CANCELS1_SEM`
L2 OZQ Cancels (Specific Reason Set 2) -- caused by an acquire	`L2_OZQ_CANCELS1-ST_FILL_CONF`	`L2_OZQ_CANCELS1.ST_FILL_CONF`	`L2_OZQ_CANCELS1_ST_FILL_CONF`
L2 OZQ Cancels (Specific Reason Set 2) -- caused by a canceled store in L2C	`L2_OZQ_CANCELS1-SYNC`	`L2_OZQ_CANCELS1.SYNC`	`L2_OZQ_CANCELS1_SYNC`
L2 OZQ Cancels (Specific Reason Set 2) -- caused by a canceled store in L2D	`L2_OZQ_CANCELS2-ACQ`	`L2_OZQ_CANCELS2.ACQ`	`L2_OZQ_CANCELS2_ACQ`
L2 OZQ Cancels (Specific Reason Set 2) -- caused because it did not recirculate	`L2_OZQ_CANCELS2-CANC_L2C_ST`	`L2_OZQ_CANCELS2.CANC_L2C_ST`	`L2_OZQ_CANCELS2_CANC_L2C_ST`
L2 OZQ Cancels (Specific Reason Set 2) -- a demand ifetch	`L2_OZQ_CANCELS2-CANC_L2D_ST`	`L2_OZQ_CANCELS2.CANC_L2D_ST`	`L2_OZQ_CANCELS2_CANC_L2D_ST`
L2 OZQ Cancels (Specific Reason Set 2) -- a store match in L2C	`L2_OZQ_CANCELS2-DIDNT_RECIRC`	`L2_OZQ_CANCELS2.DIDNT_RECIRC`	`L2_OZQ_CANCELS2_DIDNT_RECIRC`
L2 OZQ Cancels (Specific Reason Set 2) -- a L2fill and store conflict in L2C	`L2_OZQ_CANCELS2-D_IFET`	`L2_OZQ_CANCELS2.D_IFET`	`L2_OZQ_CANCELS2_D_IFET`
L2 OZQ Cancels (Specific Reason Set 2) -- oversubscription	`L2_OZQ_CANCELS2-L2C_ST_MAT`	`L2_OZQ_CANCELS2.L2C_ST_MAT`	`L2_OZQ_CANCELS2_L2C_ST_MAT`
L2 OZQ Cancels (Specific Reason Set 2) -- an OZ data conflict	`L2_OZQ_CANCELS2-L2FILL_ST_CONF`	`L2_OZQ_CANCELS2.L2FILL_ST_CONF`	`L2_OZQ_CANCELS2_L2FILL_ST_CONF`
	`L2_OZQ_CANCELS2-NONE1`
	`L2_OZQ_CANCELS2-NONE2`
	`L2_OZQ_CANCELS2-NONE3`
	`L2_OZQ_CANCELS2-OVER_SUB`	`L2_OZQ_CANCELS2.OVER_SUB`	`L2_OZQ_CANCELS2_OVER_SUB`
	`L2_OZQ_CANCELS2-OZ_DATA_CONF`	`L2_OZQ_CANCELS2.OZ_DATA_CONF`	`L2_OZQ_CANCELS2_OZ_DATA_CONF`
L2 OZQ Cancels (Specific Reason Set 2) -- a write back conflict (canceling read?)	`L2_OZQ_CANCELS2-READ_WB_CONF`	`L2_OZQ_CANCELS2.READ_WB_CONF`	`L2_OZQ_CANCELS2_READ_WB_CONF`
L2 OZQ Cancels (Specific Reason Set 2) -- caused by a recirculate oversubscription	`L2_OZQ_CANCELS2-RECIRC_ OVER_SUB`	`L2_OZQ_CANCELS2.RECIRC_ OVER_SUB`	`L2_OZQ_CANCELS2_RECIRC_ OVER_SUB`
L2 OZQ Cancels (Specific Reason Set 2) -- 32/64 byte HPW/L2D fill which needs scrub	`L2_OZQ_CANCELS2-SCRUB`	`L2_OZQ_CANCELS2.SCRUB`	`L2_OZQ_CANCELS2_SCRUB`
L2 OZQ Cancels (Specific Reason Set 2) -- counts the cancels caused by attempted 5-cycle bypasses for non-aligned accesses and bypasses blocking recirculates for too long	`L2_OZQ_CANCELS2-WEIRD`	`L2_OZQ_CANCELS2.WEIRD`	`L2_OZQ_CANCELS2_WEIRD`
L2D OZQ Is Full -- L2D OZQ is full	`L2_OZQ_FULL-THIS`	`L2_OZQ_FULL.THIS`	`L2_OZQ_FULL_THIS`
Clocks With Release Ordering Attribute Existed in L2 OZQ	`L2_OZQ_RELEASE`	`L2_OZQ_RELEASE`	`L2_OZQ_RELEASE`
Requests Made To L2	`L2_REFERENCES`	`L2_REFERENCES`	`L2_REFERENCES`
Store Hit a Shared Line -- Store hit a shared line	`L2_STORE_HIT_SHARED-ANY`	`L2_STORE_HIT_SHARED.ANY`	`L2_STORE_HIT_SHARED_ANY`
Synthesized Probe	`L2_SYNTH_PROBE`	`L2_SYNTH_PROBE`	`L2_SYNTH_PROBE`
L2D Victim Buffer Is Full -- L2D victim buffer is full	`L2_VICTIMB_FULL-THIS`	`L2_VICTIMB_FULL.THIS`	`L2_VICTIMB_FULL_THIS`
L3 Cache Lines Replaced	`L3_LINES_REPLACED`	`L3_LINES_REPLACED`	`L3_LINES_REPLACED`
L3 Misses	`L3_MISSES`	`L3_MISSES`	`L3_MISSES`
L3 Reads -- L3 Read References	`L3_READS-ALL-ALL`	`L3_READS.ALL.ALL`	`L3_READS_ALL_ALL`
L3 Reads -- L3 Read Hits	`L3_READS-ALL-HIT`	`L3_READS.ALL.HIT`	`L3_READS_ALL_HIT`
L3 Reads -- L3 Read Misses	`L3_READS-ALL-MISS`	`L3_READS.ALL.MISS`	`L3_READS_ALL_MISS`
	`L3_READS-ALL-NONE`
L3 Reads -- L3 Load References (excludes reads for ownership used to satisfy stores)	`L3_READS-DATA_READ-ALL`	`L3_READS.DATA_READ.ALL`	`L3_READS_DATA_READ_ALL`
L3 Reads -- L3 Load Hits (excludes reads for ownership used to satisfy stores)	`L3_READS-DATA_READ-HIT`	`L3_READS.DATA_READ.HIT`	`L3_READS_DATA_READ_HIT`
L3 Reads -- L3 Load Misses (excludes reads for ownership used to satisfy stores)	`L3_READS-DATA_READ-MISS`	`L3_READS.DATA_READ.MISS`	`L3_READS_DATA_READ_MISS`
	`L3_READS-DATA_READ-NONE`
L3 Reads -- L3 Demand Instruction References	`L3_READS-DINST_FETCH-ALL`	`L3_READS.DINST_FETCH.ALL`	`L3_READS_DINST_FETCH_ALL`
L3 Reads -- L3 Demand Instruction Fetch Hits	`L3_READS-DINST_FETCH-HIT`	`L3_READS.DINST_FETCH.HIT`	`L3_READS_DINST_FETCH_HIT`
L3 Reads -- L3 Demand Instruction Fetch Misses	`L3_READS-DINST_FETCH-MISS`	`L3_READS.DINST_FETCH.MISS`	`L3_READS_DINST_FETCH_MISS`
	`L3_READS-DINST_FETCH-NONE`
L3 Reads -- L3 Instruction Fetch and Prefetch References	`L3_READS-INST_FETCH-ALL`	`L3_READS.INST_FETCH.ALL`	`L3_READS_INST_FETCH_ALL`
L3 Reads -- L3 Instruction Fetch and Prefetch Hits	`L3_READS-INST_FETCH-HIT`	`L3_READS.INST_FETCH.HIT`	`L3_READS_INST_FETCH_HIT`
L3 Reads -- L3 Instruction Fetch and Prefetch Misses	`L3_READS-INST_FETCH-MISS`	`L3_READS.INST_FETCH.MISS`	`L3_READS_INST_FETCH_MISS`
	`L3_READS-INST_FETCH-NONE`
L3 References	`L3_REFERENCES`	`L3_REFERENCES`	`L3_REFERENCES`
L3 Writes -- L3 Write References	`L3_WRITES-ALL-ALL`	`L3_WRITES.ALL.ALL`	`L3_WRITES_ALL_ALL`
L3 Writes -- L3 Write Hits	`L3_WRITES-ALL-HIT`	`L3_WRITES.ALL.HIT`	`L3_WRITES_ALL_HIT`
L3 Writes -- L3 Write Misses	`L3_WRITES-ALL-MISS`	`L3_WRITES.ALL.MISS`	`L3_WRITES_ALL_MISS`
	`L3_WRITES-ALL-NONE`
L3 Writes -- L3 Store References (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)	`L3_WRITES-DATA_WRITE-ALL`	`L3_WRITES.DATA_WRITE.ALL`	`L3_WRITES_DATA_WRITE_ALL`
L3 Writes -- L3 Store Hits (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)	`L3_WRITES-DATA_WRITE-HIT`	`L3_WRITES.DATA_WRITE.HIT`	`L3_WRITES_DATA_WRITE_HIT`
L3 Writes -- L3 Store Misses (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)	`L3_WRITES-DATA_WRITE-MISS`	`L3_WRITES.DATA_WRITE.MISS`	`L3_WRITES_DATA_WRITE_MISS`
	`L3_WRITES-DATA_WRITE-NONE`
L3 Writes -- L2 Write Back References	`L3_WRITES-L2_WB-ALL`	`L3_WRITES.L2_WB.ALL`	`L3_WRITES_L2_WB_ALL`
`L3 Writes -- L2 Write Back Hits`	`L3_WRITES-L2_WB-HIT`	`L3_WRITES.L2_WB.HIT`	`L3_WRITES_L2_WB_HIT`
L3 Writes -- L2 Write Back Misses	`L3_WRITES-L2_WB-MISS`	`L3_WRITES.L2_WB.MISS`	`L3_WRITES_L2_WB_MISS`
	`L3_WRITES-L2_WB-NONE`
	`L3_WRITES-NONE-NONE`
Retired Loads Retired Misaligned Load Instructions Retired Uncacheable Loads	`LOADS_RETIRED`	`LOADS_RETIRED`	`LOADS_RETIRED`
Current Mem Read Transactions On Bus -- CPU or non-CPU (all transactions).	`MEM_READ_CURRENT-ANY`	`MEM_READ_CURRENT.ANY`	`MEM_READ_CURRENT_ANY`
Current Mem Read Transactions On Bus -- non-CPU priority agents	`MEM_READ_CURRENT-IO`	`MEM_READ_CURRENT.IO`	`MEM_READ_CURRENT_IO`
Retired Misaligned Load Instructions	`MEM_READ_CURRENT-NONE`
	`MEM_READ_CURRENT-SELF`
Retired Misaligned Store Instructions	`MISALIGNED_LOADS_RETIRED`	`MISALIGNED_LOADS_RETIRED`	`MISALIGNED_LOADS_RETIRED`
	`MISALIGNED_STORES_RETIRED`	`MISALIGNED_STORES_RETIRED`	`MISALIGNED_STORES_RETIRED`
Retired NOP Instructions	`NOPS_RETIRED`	`NOPS_RETIRED`	`NOPS_RETIRED`
Instructions Squashed Due to Predicate Off	`PREDICATE_SQUASHED_RETIRED`	`PREDICATE_SQUASHED_RETIRED`	`PREDICATE_SQUASHED_RETIRED`
Current RSE Registers (Bits 2:0)	`RSE_CURRENT_REGS_2_TO_0`	`RSE_CURRENT_REGS_2_TO_0`	`RSE_CURRENT_REGS_2_TO_0`
Current RSE Registers (Bits 5:3)	`RSE_CURRENT_REGS_5_TO_3`	`RSE_CURRENT_REGS_5_TO_3`	`RSE_CURRENT_REGS_5_TO_3`
Current RSE Registers (Bit 6)	`RSE_CURRENT_REGS_6`	`RSE_CURRENT_REGS_6`	`RSE_CURRENT_REGS_6`
Dirty RSE Registers (Bits 2:0)	`RSE_DIRTY_REGS_2_TO_0`	`RSE_DIRTY_REGS_2_TO_0`	`RSE_DIRTY_REGS_2_TO_0`
Dirty RSE Registers (Bits 5:3)	`RSE_DIRTY_REGS_5_TO_3`	`RSE_DIRTY_REGS_5_TO_3`	`RSE_DIRTY_REGS_5_TO_3`
Dirty RSE Registers (Bit 6)	`RSE_DIRTY_REGS_6`	`RSE_DIRTY_REGS_6`	`RSE_DIRTY_REGS_6`
Retired RSE operations	`RSE_EVENT_RETIRED`	`RSE_EVENT_RETIRED`	`RSE_EVENT_RETIRED`
RSE Accesses -- Both RSE loads and stores will be counted.	`RSE_REFERENCES_RETIRED-ALL`	`RSE_REFERENCES_RETIRED.ALL`	`RSE_REFERENCES_RETIRED_ALL`
RSE Accesses -- Only RSE loads will be counted.	`RSE_REFERENCES_RETIRED-LOAD`	`RSE_REFERENCES_RETIRED.LOAD`	`RSE_REFERENCES_RETIRED_LOAD`
	`RSE_REFERENCES_RETIRED-NONE`
RSE Accesses -- Only RSE stores will be counted.	`RSE_REFERENCES_RETIRED-STORE`	`RSE_REFERENCES_RETIRED.STORE`	`RSE_REFERENCES_RETIRED_STORE`
Number of srlz.i Instructions	`SERIALIZATION_EVENTS`	`SERIALIZATION_EVENTS`	`SERIALIZATION_EVENTS`
Retired Misaligned Store Instructions Retired Stores Retired Uncacheable Stores	`STORES_RETIRED`	`STORES_RETIRED`	`STORES_RETIRED`
Syllables Not Dispersed.	`SYLL_NOT_DISPERSED-ALL`	`SYLL_NOT_DISPERSED.ALL`	`SYLL_NOT_DISPERSED_ALL`
Syllables Not Dispersed.	`SYLL_NOT_DISPERSED-EXPL`	`SYLL_NOT_DISPERSED.EXPL`	`SYLL_NOT_DISPERSED_EXPL`
Syllables Not Dispersed.			`SYLL_NOT_DISPERSED_EXPL_OR_FE`
Syllables Not Dispersed.			`SYLL_NOT_DISPERSED_EXPL_OR_ FE_OR_MLI`
Syllables Not Dispersed.			`SYLL_NOT_DISPERSED_EXPL_OR_ IMPL`
Syllables Not Dispersed.			`SYLL_NOT_DISPERSED_EXPL_OR_ IMPL_OR_FE`
Syllables Not Dispersed.			`SYLL_NOT_DISPERSED_EXPL_OR_ IMPL_OR_MLI`
Syllables Not Dispersed.			`SYLL_NOT_DISPERSED_EXPL_OR_ MLI`
Syllables Not Dispersed.	`SYLL_NOT_DISPERSED-FE`	`SYLL_NOT_DISPERSED.FE`	`SYLL_NOT_DISPERSED_FE`
Syllables Not Dispersed.			`SYLL_NOT_DISPERSED_FE_ OR_MLI`
Syllables Not Dispersed.	`SYLL_NOT_DISPERSED-IMPL`	`SYLL_NOT_DISPERSED.IMPL`	`SYLL_NOT_DISPERSED_IMPL`
Syllables Not Dispersed.			`SYLL_NOT_DISPERSED_ IMPL_OR_FE`
Syllables Not Dispersed.			`SYLL_NOT_DISPERSED_IMPL_ OR_FE_OR_MLI`
Syllables Not Dispersed.			`SYLL_NOT_DISPERSED_ IMPL_OR_MLI`
Syllables Not Dispersed.	`SYLL_NOT_DISPERSED-MLI`	`SYLL_NOT_DISPERSED.MLI`	`SYLL_NOT_DISPERSED_MLI`
Syllables Not Dispersed.	`SYLL_OVERCOUNT-ALL`	`SYLL_OVERCOUNT.ALL`	`SYLL_OVERCOUNT_ALL`
Syllables Not Dispersed.	`SYLL_OVERCOUNT-EXPL`	`SYLL_OVERCOUNT.EXPL`	`SYLL_OVERCOUNT_EXPL`
Syllables Not Dispersed.	`SYLL_OVERCOUNT-IMPL`	`SYLL_OVERCOUNT.IMPL`	`SYLL_OVERCOUNT_IMPL`
	`SYLL_OVERCOUNT-NONE`
Retired Uncacheable Loads	`UC_LOADS_RETIRED`	`UC_LOADS_RETIRED`	`UC_LOADS_RETIRED`
Retired Uncacheable Stores	`UC_STORES_RETIRED`	`UC_STORES_RETIRED`	`UC_STORES_RETIRED`

Information for ...

Performance Counters Complete List