Intel MIC Programming Workshop
|Date:||Monday, June 27, 2016 9:00 - Wednesday, June 29, 2016, 18:00|
LRZ Building, University campus Garching, near Munich, Seminarraum 1
© Alessandro Podo, LRZ, high resolution here
The course discusses Intel’s new Many Integrated Core (MIC) architecture. It covers various programming and optimisation techniques for Intel Xeon Phi coprocessors.
The first 2 days provide an introduction about the Intel KNC architecture and various Intel Xeon Phi programming models, interleaved with many hands-on sessions. The hands-on sessions are done on the SuperMIC system at LRZ.
The last day presents advanced topics and talks about the recently launched KNL architecture. In a plenary session invited speakers talk about experiences and best practices using Intel Xeon Phi based systems like e.g. Salomon @ IT4Innovations (Czech Republic), the largest Intel Xeon Phi based system in Europe.
About the tutors
Momme Allalen received his Ph.D in theoretical Physics from the University of Osnabrück in 2006. He worked in the field of molecular magnetics through modelling techniques such as the exact numerical diagonalisation of the Heisenberg model. He joined the Leibniz Computing Centre (LRZ) in 2007 working in the High Performance Computing group. His tasks include user support, optimisation and parallelisation of scientific application codes, and benchmarking for characterising and evaluating the performance of high-end supercomputers. His research interests are various aspects of parallel computing and new programming languages and paradigms.
Fabio Baruffa was working as HPC researcher at MPCDF, Jülich Research Center and Cineca involved in software development and analysis of scientific code before joining LRZ as HPC Application Specialist in 2016. His main research interests are in the area of computational methods and optimization for HPC systems. He holds a PhD in Physics from University of Regensburg for his research in the area of Spintronics device and quantum computing.
Volker Weinberg studied physics at the Ludwig Maximilian University of Munich and later worked at the research centre DESY. He received his PhD from the Free University of Berlin for his studies in the field of lattice QCD. Since 2008 he is working in the HPC group at the Leibniz Supercomputing Centre and is responsible for HPC and PATC (PRACE Advanced Training Centre) courses at LRZ, new programming languages and the Intel Xeon Phi based system SuperMIC. Within PRACE-4IP he took over the leadership to create Best Practice Guides for new architectures and systems.
Monday, June 27, 2016, Seminarraum 1, H.E.008
Tuesday, June 28, 2016, Seminarraum 1, H.E.008
Wednesday, June 29, 2016, 09:00-12:00, Hörsaal, H.E.009 (Lecture Hall), public session
Wednesday, June 29, 2016, 13:00-18:00, Hörsaal, H.E.009 (Lecture Hall)
Plenum session with invited talks on MIC experience and best practice recommendations
The course material is developed within PRACE and the joint German-Czech Republic project CzeBaCCA. The plenum session is also part of a three-day scientific workshop on "High Performance Computing for Water Related Hazards" of this project taking place at LRZ on June 29 - July 1, 2016.
|Prerequisites||Good working knowledge of at least one of the standard HPC languages: C, C++ or Fortran. Basic OpenMP and MPI knowledge useful. Please bring your own laptop for the hands-on sessions.|
|Teachers:||Volker Weinberg, Momme Allalen, Fabio Baruffa (Leibniz Supercomputing Centre), Jan Eitzinger (RRZE), invited speakers|
|Contact:||Dr. Volker Weinberg (LRZ)|