Intel MIC Programming Workshop

Date: Monday, June 27, 2016 9:00 - Wednesday, June 29, 2016, 18:00
Location:
LRZ Building, University campus Garching, near Munich, Seminarraum 1
Contents:

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© Alessandro Podo, LRZ, high resolution here

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© LRZ

Contents

The course discusses Intel’s new Many Integrated Core (MIC) architecture. It covers various programming and optimisation techniques for Intel Xeon Phi coprocessors.

The first 2 days provide an introduction about the Intel KNC architecture and various Intel Xeon Phi programming models, interleaved with many hands-on sessions. The hands-on sessions are done on the SuperMIC system at LRZ.

The last day presents advanced topics and talks about the recently launched KNL architecture.  In a plenary session invited speakers talk about experiences and best practices using Intel Xeon Phi based systems like e.g. Salomon @ IT4Innovations (Czech Republic), the largest Intel Xeon Phi based system in Europe.

About the tutors

Momme Allalen received his Ph.D in theoretical Physics from the University of Osnabrück in 2006. He worked in the field of molecular magnetics through modelling techniques such as the exact numerical diagonalisation of the Heisenberg model. He joined the Leibniz Computing Centre (LRZ) in 2007 working in the High Performance Computing group. His tasks include user support, optimisation and parallelisation of scientific application codes, and benchmarking for characterising and evaluating the performance of high-end supercomputers. His research interests are various aspects of parallel computing and new programming languages and paradigms.

Fabio Baruffa was working as HPC researcher at MPCDF, Jülich Research Center and Cineca involved in software development and analysis of scientific code before joining LRZ as HPC Application Specialist in 2016. His main research interests are in the area of computational methods and optimization for HPC systems. He holds a PhD in Physics from University of Regensburg for his research in the area of Spintronics device and quantum computing.

Volker Weinberg studied physics at the Ludwig Maximilian University of Munich and later worked at the research centre DESY. He received his PhD from the Free University of Berlin for his studies in the field of lattice QCD. Since 2008 he is working in the HPC group at the Leibniz Supercomputing Centre and is responsible for HPC and PATC (PRACE Advanced Training Centre) courses at LRZ, new programming languages and the Intel Xeon Phi based system SuperMIC. Within PRACE-4IP he took over the leadership to create Best Practice Guides for new architectures and systems.

Preliminary schedule

 Monday, June  27,  2016, Seminarraum 1, H.E.008

  • 09:00-10:00 Introduction (Weinberg)
  • 10:00-10:30 Hardware Overview and Native I (Allalen)
  • 10:30-11:00 Coffee Break
  • 11:00-11:30 Hardware Overview and Native II (Allalen)
  • 11:30-12:00 Lab: Native Mode
  • 12:00-13:00 Lunch Break
  • 13:00-14:00 Offloading Part I (Weinberg)
  • 14:00-15:00 Lab: Offloading I
  • 15:00-15:30 Coffee Break
  • 15:30-16:15 Offloading Part II (Weinberg)
  • 16:15-17:00 Lab: Offloading II

Tuesday, June  28,  2016,  Seminarraum 1, H.E.008

  • 09:00-09:30 MPI (Weinberg)
  • 09:30-10:30 Lab: MPI
  • 10:30-11:00 Coffee Break
  • 11:00-11:30 MKL (Allalen)
  • 11:30-12:00 Lab: MKL I
  • 12:00-13:00 Lunch break
  • 13:00-13:30 Lab: MKL II
  • 13:30-14:00 Vectorisation & Performance (Allalen)
  • 14:00-15:00 Lab: Vectorisation
  • 15:00-15:30 Coffee Break
  • 15:30-17:30 Tools for Intel Xeon Phi (Baruffa)
  • 18:00 Bus leaving in front of main entrance for social event: Guided tour of Weihenstephan Brewery and dinner
  • 22:00 Bus leaving at Weihenstephan

Wednesday, June  29,  2016, 09:00-12:00, Hörsaal, H.E.009 (Lecture Hall), public session

  • 09:00-10:30 Advanced MIC Programming Techniques (SIMD, Intrinsics,... ) (Jan Eitzinger, RRZE)
  • 10:30-10:45 Coffee Break
  • 10:45-12:00 Knights Landing (KNL) architecture and software (Andrey Semin, Intel)
  • 12:00-13:00 Lunch break

Wednesday, June  29,  2016, 13:00-18:00, Hörsaal, H.E.009 (Lecture Hall)

Plenum session with invited talks on MIC experience and best practice recommendations
(joint session with the Scientific Workshop "High Performance Computing for Water Related Hazards"), public session

  • 13:00-13:45 Andrey Semin, Intel: "Intel Xeon Phi (Knights Landing) optimisation best known methods"
  • 13:45-14:30 Jan Eitzinger, RRZE: "Evaluation of Intel Xeon Phi "Knights Corner": Opportunities and Shortcomings"
  • 14:30-14:45 Coffee Break
  • 14:45-15:30 Serhiy Mochalskyy, IPP: "Simulation using MIC co-processor on HELIOS"
  • 15:30-16:15 Vit Vondrak, IT4Innovations: "ESPRESO solver based on hybrid FETI method on MIC architecture"
  • 16:15-16:30 Coffee Break
  • 16:30-17:15 Michael Bader, IPCC@TUM: "Experiences with earthquake and tsunami simulation on Xeon Phi platforms"
  • 17:15-18:00 Luigi Iapichino / Fabio Baruffa, IPCC@LRZ: "Towards modernisation of the Gadget code on many-core architectures"

The course material is developed within PRACE and the joint German-Czech Republic project CzeBaCCA. The plenum session is also part of a three-day scientific workshop on "High Performance Computing for Water Related Hazards" of this project taking place at LRZ on June 29 - July 1, 2016.

Course material

Day 1

Introduction

Hardware Overview & Native

Offloading

Lab: Native & Offload 1

Lab: Native & Offload 2


Day 2

MPI

Lab: MPI, IMB Users Guide

MKL 

Labs: mkl1, mkl2, mkl3

Basic Vectorisation & Performance

Lab: Vectorisation

Tools for Intel Xeon Phi: VTune & Advisor


Day 3

Andrey Semin, Intel: "Intel Xeon Phi (Knights Landing) optimisation best known methods"

Jan Eitzinger, RRZE: "Evaluation of Intel Xeon Phi "Knights Corner": Opportunities and Shortcomings"

Serhiy Mochalskyy, IPP: "Simulation using MIC co-processor on HELIOS"

Vit Vondrak, IT4Innovations: "ESPRESO solver based on hybrid FETI method on MIC architecture"

Michael Bader, IPCC@TUM: "Experiences with earthquake and tsunami simulation on Xeon Phi platforms"

Luigi Iapichino / Fabio Baruffa, IPCC@LRZ: "Towards modernisation of the Gadget code on many-core architectures"

Acknowledgements

       

Prerequisites Good working knowledge of at least one of the standard HPC languages: C, C++ or Fortran. Basic OpenMP and MPI knowledge useful. Please bring your own laptop for the hands-on sessions.
Language: English
Teachers: Volker Weinberg, Momme Allalen, Fabio Baruffa (Leibniz Supercomputing Centre), Jan Eitzinger (RRZE), invited speakers
Contact: Dr. Volker Weinberg (LRZ)