Intel MIC and GPU Programming Workshop
The course discusses the architecture of GPGPUs and Intel’s new Many Integrated Core (MIC) architecture.
It covers various programming and optimisation techniques for GPGPUs and Intel’s new Intel Xeon Phi coprocessors.
The hands-on sessions are done on the new Intel Xeon Phi based SuperMIC system and the GPU cluster at LRZ.
The workshop is a PRACE Advanced Training Centres (PATC) course. It is developed in collaboration with the Erlangen Regional Computing Centre (RRZE) within KONWIHR.
Each day is comprised of approximately 5 hours of lectures and 3 hours of hands-on sessions.
Contact: Dr. Volker Weinberg (mailto:firstname.lastname@example.org)
Participants 2015: (high resolution)
Foto: Vasileios Karakasis
Participants 2014: (high resolution)
- Dr. Momme Allalen, LRZ
- Dr. David Brayford, LRZ
- Dr. Ferdiand Jamitzky, LRZ
- Dr.-Ing. Michael Klemm, Intel
- Dr.-Ing. Jan Eitzinger, RRZE
- Dr. Volker Weinberg, LRZ
Day 1 Material
Day 2 Material
Day 3 Material
Please fill out the course evaluation form before leaving the lecture room to help us and PRACE to increase the quality of PATC trainings.
Thank you for your collaboration and thank you for joining our course!!
LRZ is part of the Gauss Centre for Supercomputing (GCS), which is one of the six PRACE Advanced Training Centres (PATCs) that started in 2012.
Information on further HPC courses: