Introduction to Intel FPGA Programming Models

Date: Tuesday, May 21, 2019, 09:00-17:00
Location: LRZ Building, University campus Garching, near Munich, Seminarraum 1, H.E.008

Contents:

fpga-workshop

FPGAs can help accelerate many of the core data center workloads that process the growing volume of data that our hyper-connected world creates. They can be reprogrammed in a fraction of a second with a datapath that exactly matches your workload’s key algorithms. This versatility results in a higher performing, more power efficient, and well utilized data center – lowering your total cost of ownership. FPGAS can be connected directly to processors, memories, networks, and numerous other interfaces. Traditionally, FPGAs require deep domain expertise to program for, but Intel is investing in significantly simplifying the development flow and enable rapid deployment across the data center.

This full day course offered by Intel in cooperation with LRZ is a high-level overview of FPGAs with the intention of level setting people on what they are, why they are so important as accelerators, what their programming models are and how easily they can be adopted into compute clusters through the use of the Acceleration Stack for Intel® Xeon® CPU with FPGAs.  This course contains both lecture and lab exercises to help gain familiarity with these concepts using the tools available for FPGA developers such as Quartus, Platform Designer, High Level Synthesis, OpenCL, and DSP Builder.

At completion you will have learned:

  • Why FPGA accelerators are so important in solving tomorrows problems
  • Identify the various programming models for the FPGA
  • Understand the components of the Acceleration Stack and where to get them and how to use them
  • Explain the software development model for writing software applications using the OPAE layer to run acceleration workloads on an FPGA accelerator
  • Where to get or how to create accelerator workloads for Programmable Accelerator Cards (PAC) using the Acceleration Stack for Intel® Xeon® CPU with FPGAs


Tentative Agenda:

  • Introduction to FPGAs
  • FPGA Programming Models: RTL
  • FPGA Programming Models: HLS
  • Lunch                                                     
  • FPGA Programming Models: OpenCL
  • High Performance Data Flow with FPGAs
  • Introduction to the Acceleration Stack
  • Conclusion, Q&A, Discussion


Please bring your own laptop (with an ssh client installed) for the hands-on sessions!


Prerequisites
Language: English
Teachers: Bill Jenkins (Intel)
Registration:

Via the LRZ registration form. Please choose course HFPG1S19.

Hands-on:

tbd.

Contact: Dr. Volker Weinberg (LRZ)

intel