PRACE PATC Course: HPC code optimisation workshop
|Date:||Thursday, May 4, 2017, 9:00-17:00|
|Location:||LRZ Building, University campus Garching, near Munich, Kursraum (lecture room) 2, H.U.010|
The workshop is organised as a compact course on techniques and methods, focused on code improvement and exploration of the latest Intel processor features, in particular the vector units. During this optimisation process, the attendees will learn how to enable vectorisation using simple pragmas and more effective techniques, like changing data layout and alignment. This work is guided by the hints from the Intel compiler reports, and using Intel Advisor. The outline of the workshop includes: basics on modern computer architectures, optimisation process and vectorisation, Intel Advisor. We provide also an N-body code, to support the described optimisation solutions with practical examples.
The course is a PRACE Advanced Training Center event.
Through a sequence of simple, guided examples of code modernisation, the attendees will develop awareness on features of multi and many-core architecture which are crucial for writing modern, portable and efficient applications.
09:00-10:30 Introduction: Modern computer architecture, memory hierarchy
About the lecturers
The attendees are expected to have a basic knowledge of C/C++ programming language, parallel programming (MPI, OpenMP) and use of compilers, mainly Intel. A basic knowledge of Linux, Unix or Mac OS X (e.g. simple shell commands) is also beneficial.
|Teachers:||Dr. Fabio Baruffa, Dr. Luigi Iapichino (LRZ)|
The exercises will be done on the SuperMIC system at LRZ.
|Contact:||Dr. Volker Weinberg (LRZ)|