SuperMUC 4th Extreme Scaling Workshop

Deadline for proposal submission: Feb 1st, 2016

In Feb 2016 LRZ will again perform a four day workshop on extreme code scaling. The goal of this workshop is to provide an opportunity for application teams to scale their code across the full SuperMUC Phase1, the 3.2 PetaFLOP/s machine at LRZ. Teams can apply for the workshop. From the applicants, the most promising software packages will be invited to the LRZ in Garching. Extreme scaling experts from Lenovo, IBM, Intel and LRZ personells will be working together with the teams to scale the software on up to the complete 140,000 cores of SuperMUC Phase1 (Sandybridge partition/segment).

As a precondition for the workshop participation the applicants must demonstrate a sufficient scaling behavior of the selected application via scaling plots for 1, 2 and 4 islands (max 32,000 cores) on SuperMUC Phase1.

Teams with already existing LRZ or PRACE accounts can use their user account to generate the necessary scaling plots up to 32,000 cores. New teams are requested to contact Ferdinand Jamitzky ( for more information on how to obtain a test account. Each team will get 100,000 cpu hours extra for the preparation of the scaling plots.

Please provide the following information in your application documents:

  • Contact Data: Name, Affiliation, e-mail, phone and project ID.
  • Name of your code and short description of it including the scientific motivation and up to 5 references.
  • Assurance that the code already scales up to 32,000 cores (provide a scaling plot for 1,2 and 4 islands on SuperMUC)
  • Time needed for a single test run (should be typically less than 0.5 h) 
  • Memory usage per core (< 1.6 GB/core is required) 
  • Hard disk data usage (should be < 1 TB) 
  • Other code requirements (libraries, I/O, compiler versions, etc).

By submitting an application all applicants automatically agree, that – in case their application will be selected – they will provide a two-page summary to LRZ not later than two weeks after the workshop, including a list of authors, scaling plots, profiling results (GFlop/s, I/O bandwidth). LRZ will compile these summaries for publication of a joint paper in a high profile HPC magazine.