IPCC Intel Xeon Phi Coprocessor Workshop
|Date:||October 20 - 21, 2014 9:30 - 17:30|
|Location:||LRZ Building, Garching/Munich, Boltzmannstr. 1|
This workshop is part of the LRZ activities as an Intel Parallel Computing
Center(IPCC) and it is organized together with Intel.
The following items serve as suggestions for workshop content. Analysis tools should be applied to IPCC codes. Intel engineers will be available supporting this effort. Some base information will be given before each lab session as a startup.
Emphasis of this workshop will be “hands on” the IPCC codes. Basic knowledge of Xeon Phi™ programming concepts should be available.
A potential procedure is to have 45 minutes of lectures followed by 2 hours of labs. We may also split the audience into groups of different topics.
|Prerequisites||This is an advanced level course. The applicants should have good knowledge about MPI, Intel compilers and also some working experience with the Intel MIC architecture.|
Please send your request to Anupam Karmakar (Email: karmakar_at_lrz.de) till October 12, 2014 with Subject: Course HMIC1W14. The number of participants is limited to 6 and offered on a first come, first served basis.