PRACE Fourth Implementation Phase Project (PRACE-4IP)

PRACE Logo

The purpose of the PRACE Research Infrastructure is to provide a sustainable high-quality infrastructure for Europe that can meet the most demanding needs of European HPC user communities through the provision of user access to the most powerful HPC systems available worldwide at any given time. In tandem with access to Tier-0 systems, the PRACE project will foster the coordination between national HPC resources (Tier-1 systems) to best meet the needs of the European HPC user community.

PRACE-4IP is designed to build on and seamlessly continue the successes of the Partnership for Advanced Computing in Europe (PRACE) and start new innovative and collaborative activities. These include: assisting the transition to PRACE 2; strengthening the internationally recognised PRACE brand; preparing strategies and best practices towards exascale computing, coordinating and enhancing the operation of the multi-tier HPC systems and services, and supporting and educating users to exploit massively parallel systems and novel architectures.

Objectives

  • Ensure long-term sustainability of the infrastructure.
  • Promote Europe’s leadership in HPC applications.
  • Increase European human resources skilled in HPC and HPC applications.
  • Support a balanced eco-system of HPC resources for Europe’s researchers.
  • Evaluate new technologies and support Europe’s path for using ExaFlop/s resources.
  • Disseminate effectively the PRACE results.

LRZ is involved in the following workpackages:

  • WP4: Training
  • WP5: HPC Commissioning and Prototyping
  • WP7: Application Enabling and Support

Highlights

Within WP7 four new Best Practice Guides have been published under the leadership of LRZ: Intel Xeon Phi, Knights Landing,Haswell/Broadwell and GPGPU, see http://www.prace-ri.eu/best-practice-guides/

Events

  • PRACE PATC Course: Introduction to hybrid programming in HPC, LRZ, 14.1.2016
  • PRACE PATC Course: Advanced Topics in High Performance Computing, LRZ, 4.-7.4.2016
  • PRACE PATC Workshop: 21st VI-HPS Tuning Workshop, LRZ, 18.-22.4.2016
  • 7th European Workshop on HPC Centre Infrastructures, LRZ, 19.-22.4.2016
  • PRACE PATC Course: Intel MIC Programming Workshop, LRZ, 27.-29.6.2016
  • PRACE PATC Course: Advanced Fortran Topics, LRZ, 12.-16.9.2016
  • PRACE PATC Course: Node-Level Performance Engineering, LRZ, 1.-2.12.2016

Publications

Sgattoni, A., Fedeli, L., Sinigardi, S., Marocchino, A., Macchi, A., Weinberg, V., Karmakar, A.: Optimising PICCANTE - an Open Source Particle-in-Cell Code for Advanced Simulations on Tier-0 Systems. In: arXiv:1503.02464 [cs.DC], 2015.

Weinberg, V., Allalen, M.: 2nd Intel MIC & GPU Programming Workshop at LRZ. In: inSIDE, Vol. 13, No. 2, p. 79, 2015.

Emanouil Atanassov, Michaela Barth, Mikko Byckling, Vali Codreanu, Nevena Ilieva, Tomáš Karásek, Jorge Rodriguez, Sami Saarinen, Ole Widar Saastad, Michael Schliephake, Martin Stachoň, Janko Strassburg, and Volker Weinberg (Editor), Best Practice Guide – Intel® Xeon Phi™ v2.0, http://www.prace-ri.eu/best-practice-guides/, January 2017

Vali Codreanu, Joerg Hertzer, Christian Morales, Jorge Rodriguez, Ole Widar Saastad, Martin Stachoň, and Volker Weinberg (Editor), Best Practice Guide – Haswell/Broadwell,  http://www.prace-ri.eu/best-practice-guides/, January 2017

Momme Allalen, Alan Gray (Editor), Nevena Ilieva-Litova, Anders Sjöström, Vali Codreanu, and Volker Weinberg, Best Practice Guide – GPGPU, http://www.prace-ri.eu/best-practice-guides/, January 2017

Volker Weinberg, Alan Gray, Ole Widar Saastad, Best Practice Guides for New and Emerging Architectures, PRACE D7.6, January 2017

Fast Facts

Project Duration

01/02/2015 – 30/04/2017

Contact persons

Dr. Michael Ott
Dr. Volker Weinberg

Funding agency

European Commission FP7

Website

http://www.prace-ri.eu/prace-fourth-implementation-phase-prace-4ip-project/

Partner Institutions

  • JUELICH- Forschungszentrum Jülich GmbH (Germany, Coordinator)
  • GCS – Gauss Centre for Supercomputing (GCS) e.V. (Germany)
  • GENCI – Grand Equipement National de Calcul Intensif (France)
  • EPCC – The University of Edinburgh (United Kingdom)
  • BSC – Barcelona Supercomputing Center – Centro Nacional de Supercomputacion (Spain)
  • CSC – Tieteen Tietotekniikan Keskus OY (Finland)
  • ETHZ – Eidgenössische Technische Hochschule Zuerich (Switzerland)
  • SURFSARA BV – SURFsara BV (The Netherlands)
  • JKU – Johannes Kepler Universitaet Linz (Austria)
  • SNIC – Uppsala Universitet (Sweden)
  • CINECA Consorzio Interuniversitario (Italy)
  • PSNC – Instytut Chemii Bioorganicznej Pan WPoznaniu (Poland)
  • SIGMA2 – Uninett Sigma2 AS (Norway)
  • GRNET – Greek Research and Technology Network S.A. (Greece)
  • UC-LCA – Faculdade de Ciencias e Tecnologia da Universidade de Coimbra (Portugal)
  • NUI Galway – National University of Ireland, Galway (Ireland)
  • UYBHM – Istanbul Technical University, Ayazaga Campus (Turkey)
  • CaSToRC – The Cyprus Institute (Cyprus)
  • NCSA – National Centre for Supercomputing Applications (Bulgaria)
  • IT4I-VSB – Technical University of Ostrava (Czech Republic)
  • NIIF – Nemzeti Információs Infrastruktúra Fejlesztési Intézet (Hungary)
  • UCPH – Københavns Universitet (Denmark)
  • IUCC – Inter University Computation Center (Israel)
  • PRACE – Partnership for Advanced Computing in Europe AISBL (Belgium)
  • ULFME – University of Ljubljana, Faculty of Mechanical Engineering (Slovenia)
  • CCSAS – Computing Centre of the Slovak Academy of Sciences (Slovakia)