Introduction to Intel FPGA Programming Models
Date: Tuesday, May 21, 2019, 09:00-17:00
Lecturers: Bill Jenkins (Intel)
Further Details and Registration: https://www.lrz.de/services/compute/courses/2019-05-21_hfpg1s19/
Registration deadline: 6 May 2019
Location: LRZ Building, University campus Garching, near Munich, Germany
FPGAs can help accelerate many of the core data center workloads that process the growing volume of data that our hyper-connected world creates. They can be reprogrammed in a fraction of a second with a datapath that exactly matches your workload’s key algorithms. This versatility results in a higher performing, more power efficient, and well utilized data center – lowering your total cost of ownership. FPGAS can be connected directly to processors, memories, networks, and numerous other interfaces. Traditionally, FPGAs require deep domain expertise to program for, but Intel is investing in significantly simplifying the development flow and enable rapid deployment across the data center.
This full day course offered by Intel in cooperation with LRZ is a high-level overview of FPGAs with the intention of level setting people on what they are, why they are so important as accelerators, what their programming models are and how easily they can be adopted into compute clusters through the use of the Acceleration Stack for Intel® Xeon® CPU with FPGAs. This course contains both lecture and lab exercises to help gain familiarity with these concepts using the tools available for FPGA developers such as Quartus, Platform Designer, High Level Synthesis, OpenCL, and DSP Builder.
At completion you will have learned:
- Why FPGA accelerators are so important in solving tomorrows problems
- Identify the various programming models for the FPGA
- Understand the components of the Acceleration Stack and where to get them and how to use them
- Explain the software development model for writing software applications using the OPAE layer to run acceleration workloads on an FPGA accelerator
- Where to get or how to create accelerator workloads for Programmable Accelerator Cards (PAC) using the Acceleration Stack for Intel® Xeon® CPU with FPGAs