PAPI Event |
Description |
AMD Opteron |
Pent 4 |
PWR4 |
Itanium2 |
---|---|---|---|---|---|
PAPI_BR_CN |
Conditional branch instructions |
* |
|
|
|
PAPI_BR_INS |
Branch instructions |
2 |
* |
|
* |
PAPI_BR_MSP |
Conditional branch instructions mispredicted |
* |
* |
|
2 |
PAPI_BR_NTK |
Conditional branch instructions not taken |
2 |
* |
|
|
PAPI_BR_PRC |
Conditional branch instructions correctly predicted |
2 |
* |
|
* |
PAPI_BR_TKN |
Conditional branch instructions taken |
* |
* |
|
|
PAPI_BR_UCN |
Unconditional branch instructions |
* |
|
|
|
PAPI_BRU_IDL |
Cycles branch units are idle |
|
|
|
|
PAPI_BTAC_M |
Branch target address cache misses |
|
|
|
|
PAPI_CA_CLN |
Requests for exclusive access to clean cache line |
|
|
|
|
PAPI_CA_INV |
Requests for cache line invalidation |
|
|
|
2 |
PAPI_CA_ITV |
Requests for cache line intervention |
|
|
|
|
PAPI_CA_SHR |
Requests for exclusive access to shared cache line |
|
|
|
|
PAPI_CA_SNP |
Requests for a snoop |
|
|
|
* |
PAPI_CSR_FAL |
Failed store conditional instructions |
|
|
|
|
PAPI_CSR_SUC |
Successful store conditional instructions |
|
|
|
|
PAPI_CSR_TOT |
Total store conditional instructions |
|
|
|
|
PAPI_FAD_INS |
Floating point add instructions |
* |
|
|
|
PAPI_FDV_INS |
Floating point divide instructions |
|
|
* |
|
PAPI_FMA_INS |
FMA instructions completed |
|
|
* |
|
PAPI_FML_INS |
Floating point multiply instructions |
* |
|
|
|
PAPI_FNV_INS |
Floating point inverse instructions |
|
|
|
|
PAPI_FP_INS |
Floating point instructions |
* |
2 |
* |
|
PAPI_FP_OPS |
Floating point operations |
* |
|
4 |
* |
PAPI_FP_STAL |
Cycles the FP unit(s) are stalled |
* |
|
|
* |
PAPI_FPU_IDL |
Cycles floating point units are idle |
* |
|
|
|
PAPI_FSQ_INS |
Floating point square root instructions |
|
|
* |
|
PAPI_FUL_CCY |
Cycles with maximum instructions completed |
|
|
|
|
PAPI_FUL_ICY |
Cycles with maximum instruction issue |
|
|
|
|
PAPI_FXU_IDL |
Cycles integer units are idle |
|
|
* |
|
PAPI_HW_INT |
Hardware interrupts |
* |
|
* |
|
PAPI_INT_INS |
Integer instructions |
|
|
* |
|
PAPI_L1_DCA |
Level 1 data cache accesses |
* |
|
2 |
* |
PAPI_L1_DCH |
Level 1 data cache hits |
2 |
|
|
2 |
PAPI_L1_DCM |
Level 1 data cache misses |
* |
* |
2 |
* |
PAPI_L1_DCR |
Level 1 data cache reads |
|
|
* |
* |
PAPI_L1_DCW |
Level 1 data cache writes |
|
|
* |
|
PAPI_L1_ICA |
Level 1 instruction cache accesses |
* |
|
|
2 |
PAPI_L1_ICH |
Level 1 instruction cache hits |
|
|
|
|
PAPI_L1_ICM |
Level 1 instruction cache misses |
* |
|
|
* |
PAPI_L1_ICR |
Level 1 instruction cache reads |
* |
|
|
2 |
PAPI_L1_ICW |
Level 1 instruction cache writes |
|
|
|
|
PAPI_L1_LDM |
Level 1 load misses |
4 |
* |
* |
2 |
PAPI_L1_STM |
Level 1 store misses |
* |
|
* |
|
PAPI_L1_TCA |
Level 1 total cache accesses |
2 |
|
|
2 |
PAPI_L1_TCH |
Level 1 total cache hits |
|
|
|
|
PAPI_L1_TCM |
Level 1 cache misses |
2 |
|
|
2 |
PAPI_L1_TCR |
Level 1 total cache reads |
|
|
|
2 |
PAPI_L1_TCW |
Level 1 total cache writes |
|
|
|
|
PAPI_L2_DCA |
Level 2 data cache accesses |
* |
|
|
* |
PAPI_L2_DCH |
Level 2 data cache hits |
* |
|
|
2 |
PAPI_L2_DCM |
Level 2 data cache misses |
* |
|
* |
2 |
PAPI_L2_DCR |
Level 2 data cache reads |
3 |
* |
|
* |
PAPI_L2_DCW |
Level 2 data cache writes |
2 |
|
|
* |
PAPI_L2_ICA |
Level 2 instruction cache accesses |
* |
|
|
* |
PAPI_L2_ICH |
Level 2 instruction cache hits |
|
|
|
|
PAPI_L2_ICM |
Level 2 instruction cache misses |
* |
|
|
* |
PAPI_L2_ICR |
Level 2 instruction cache reads |
|
|
|
2 |
PAPI_L2_ICW |
Level 2 instruction cache writes |
|
|
|
|
PAPI_L2_LDM |
Level 2 load misses |
4 |
* |
|
* |
PAPI_L2_STM |
Level 2 store misses |
* |
* |
|
* |
PAPI_L2_TCA |
Level 2 total cache accesses |
|
|
|
* |
PAPI_L2_TCH |
Level 2 total cache hits |
|
|
|
2 |
PAPI_L2_TCM |
Level 2 cache misses |
2 |
* |
|
* |
PAPI_L2_TCR |
Level 2 total cache reads |
|
|
|
2 |
PAPI_L2_TCW |
Level 2 total cache writes |
|
|
|
* |
PAPI_L3_DCA |
Level 3 data cache accesses |
|
|
|
* |
PAPI_L3_DCH |
Level 3 data cache hits |
|
|
|
2 |
PAPI_L3_DCM |
Level 3 data cache misses |
|
|
|
2 |
PAPI_L3_DCR |
Level 3 data cache reads |
|
* |
|
* |
PAPI_L3_DCW |
Level 3 data cache writes |
|
|
|
* |
PAPI_L3_ICA |
Level 3 instruction cache accesses |
|
|
|
* |
PAPI_L3_ICH |
Level 3 instruction cache hits |
|
|
|
* |
PAPI_L3_ICM |
Level 3 instruction cache misses |
|
|
|
* |
PAPI_L3_ICR |
Level 3 instruction cache reads |
|
|
|
* |
PAPI_L3_ICW |
Level 3 instruction cache writes |
|
|
|
|
PAPI_L3_LDM |
Level 3 load misses |
|
* |
|
* |
PAPI_L3_STM |
Level 3 store misses |
|
|
|
* |
PAPI_L3_TCA |
Level 3 total cache accesses |
|
|
|
* |
PAPI_L3_TCH |
Level 3 total cache hits |
|
|
|
2 |
PAPI_L3_TCM |
Level 3 cache misses |
|
|
|
* |
PAPI_L3_TCR |
Level 3 total cache reads |
|
|
|
* |
PAPI_L3_TCW |
Level 3 total cache writes |
|
|
|
* |
PAPI_LD_INS |
Load instructions |
|
2 |
* |
* |
PAPI_LST_INS |
Load/store instructions completed |
|
2 |
2 |
|
PAPI_LSU_IDL |
Cycles load/store units are idle |
|
|
|
|
PAPI_MEM_RCY |
Cycles Stalled Waiting for memory Reads |
|
|
|
|
PAPI_MEM_SCY |
Cycles Stalled Waiting for memory accesses |
* |
|
|
|
PAPI_MEM_WCY |
Cycles Stalled Waiting for memory writes |
|
|
|
|
PAPI_PRF_DM |
Data prefetch cache misses |
|
|
|
|
PAPI_RES_STL |
Cycles stalled on any resource |
* |
* |
|
* |
PAPI_SR_INS |
Store instructions |
|
2 |
* |
* |
PAPI_STL_CCY |
Cycles with no instructions completed |
|
|
|
* |
PAPI_STL_ICY |
Cycles with no instruction issue |
* |
|
* |
* |
PAPI_SYC_INS |
Synchronization instructions completed |
|
|
|
|
PAPI_TLB_DM |
Data translation lookaside buffer misses |
* |
* |
* |
* |
PAPI_TLB_IM |
Instruction translation lookaside buffer misses |
* |
* |
* |
* |
PAPI_TLB_SD |
Translation lookaside buffer shootdowns |
|
|
|
|
PAPI_TLB_TL |
Total translation lookaside buffer misses |
2 |
* |
2 |
2 |
PAPI_TOT_CYC |
Total cycles |
* |
* |
* |
* |
PAPI_TOT_IIS |
Instructions issued |
|
* |
* |
* |
PAPI_TOT_INS |
Instructions completed |
* |
* |
* |
2 |
PAPI_VEC_INS |
Vector/SIMD instructions |
* |
3 SSE |
|
|