Hardware Description of HLRB II
The HLRB II is based on SGI's Altix 4700 platform. The system installed at LRZ
is optimized for high application performance and high memory bandwidth.
The following table provides an overview of the hardware and characteristics of the HLRB II.
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Overall Characteristics for both installation phases |
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Phase 1 |
Phase 2 |
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|---|---|---|---|---|
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Total number of cores |
4096 |
9728 |
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Peak Performance of the entire system |
26.2 TFlop/s |
62.3 TFlop/s |
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| Linpack Performance | 24.5 TFlop/s | 56.5 TFlop/s | ||
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Total size of memory for entire system |
17.5 TByte |
39 TByte |
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Direct Attached Disks |
300 TByte |
600 TByte |
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Network Attached Disks |
40 TByte |
60 TByte |
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Granularity |
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Number of compute partitions |
16 |
19 (13+ 6 with high density blades) |
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Number of cores per compute partition |
256 |
512 |
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Number of blades (memory channels) per compute partition |
256 |
128 (high density) or 256 |
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Number of cores per socket |
1 |
2 |
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Number of cores per blade |
1 |
2 or 4 (high density blades) |
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Processor |
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| Processor type | Intel Itanium2 Madison 9M | Intel Itanium2 Montecito Dual Core | ||
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Clock rate |
1.6 GHz |
1.6 GHz |
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Number of Floating Point Operations per clock |
4 (=2 FMAs) |
4 (=2 FMAs) |
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Peak performance of a socket |
6.4 GFlop/s |
12.8 GFlop/s |
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Max. number of Instructions per clock tick |
6 |
12 (6 per Core) |
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Peak number of instructions per second of a socket (Gip/s) |
9.6 Gip/s |
19.2 Gip/s (9.6 per Core) |
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Number of FP Registers |
128 |
256 (128 per core) |
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Memory |
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Memory per core |
4 GByte (8 GByte on interactive node) |
4 GByte per Core |
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Clock rate of frontside bus (FSB) |
533 MHz |
533 MHz |
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Peak bandwidth to local memory |
8.5 GByte/s per core |
8.5 GByte/s shared between 2 or 4 cores (density blades) |
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Total bandwidth to local memory of the entire system |
34816 GByte/s |
34816 GByte/s |
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Latency to local memory |
approx. 210 cycles |
approx. ??? cycles |
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Memory Hierarchy |
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L1 Data Cache (not used for floating point data) |
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size |
16 kByte |
16 kByte |
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cacheline size |
64 Byte |
64 Byte |
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associativity |
4-way |
4-way |
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latency |
1 cycle |
1 cycle |
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Bandwidth |
25.6 GByte/s |
25.6 GByte/s |
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L2 Data Cache (per core) |
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Size |
256 kByte |
256 kByte |
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Cacheline size |
128 Byte |
128 Byte |
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Associativity |
8-way |
8-way |
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min. Latency |
INT: 5 cycles, |
INT: 5 cycles, |
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Bandwidth |
51.2 GByte/s (FP) (+25.6 GByte/s (INT)) |
51.2 GByte/s (FP) (+25.6 GByte/s (INT)) |
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Data banks |
16 Bytes/bank |
16 Bytes/bank |
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L2 Instr. Cache (per core) |
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Size |
n/a |
1 MByte |
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L3 Cache (per core) |
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Size |
6 MByte |
9 MByte |
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Cacheline size |
128 Byte |
128 Byte |
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Associativity |
12-way |
12-way |
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min. Latency |
14 cycles |
14 cycles |
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Bandwidth |
51.2 GByte/s |
51.2 GByte/s |
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Fill Bandwidth |
128 Byte in 4 cycles |
128 Byte in 4 cycles |
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L2 Data TLB |
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Entries |
128 |
128 |
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Latency |
30 cycle penalty for TLB miss |
30 cycle penalty for |
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Internal Interconnect |
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Connection network type |
NUMAlink 4 |
NUMAlink 4 |
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Number of (bidirectional) links per blade |
2 |
2 |
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Bandwidth of one link (bidirectional) |
6.4 GByte/s |
6.4 GByte/s |
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MPI latency |
1-5 µs |
1-5 µs |
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Disks |
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Direct attached disks |
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Characteristics |
few, but large files; high bandwidth; |
few, but large files; high bandwidth Pseudo Temporary Files, Temporary Project Files |
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Size |
300 TByte |
600 TByte |
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aggr. bandwidth |
20 GByte/s |
40 GByte/s |
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Networked attached disks (Home Directories) |
30 TByte | 60 TByt | |
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Characteristics |
many, but small files; high transaction rate | many, but small files; high transaction rate | ||
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Size |
40 TByte |
60 TByte |
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bandwidth to |
600 MByte/s |
800 MByte/s |
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Environment |
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Footprint |
24 m x 12 m |
24 m x 12 m |
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Total weight |
103 metric tons |
103 metric tons |
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Total electrical power |
~1000 kVA |
~1100 kVA |
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See also: SGI's fact sheet